On Wed, Jun 21, 2023 at 03:51:18PM +0530, Nikhil M Jain wrote: > To understand usage of DDR in A53 SPL stage, add a table showing region > and space used by major components of SPL. > > Signed-off-by: Nikhil M Jain <[email protected]>
Reviewed-by: Tom Rini <[email protected]> -- Tom
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