On Wed, Jun 14, 2023 at 05:28:53PM -0500, Andreas Dannenberg wrote:
> The different CPSW sub-system Ethernet ports have different PHY mode
> control registers. In order to allow the modes to get configured
> independently only the register for the port in question must be
> accessed, otherwise we would just be re-configuring the mode for port 1,
> while leaving all others at their power-on defaults. Fix this issue by
> adding a port-number based offset to the mode control base register
> address based on the fact that the control registers for the different
> ports are spaced exactly 0x4 bytes apart.
>
> Fixes: 9d0dca1199d1 ("net: ethernet: ti: Introduce am654 gigabit eth switch
> subsystem driver")
> Signed-off-by: Andreas Dannenberg <[email protected]>
> Reviewed-by: Siddharth Vadapalli <[email protected]>Applied to u-boot/master, thanks! -- Tom
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