On 2023/7/21 16:46, Alper Nebi Yasak wrote:
Some veyron boards seem to have Winbond SPI flash chips instead of
GigaDevice ones. At the very least, coreboot builds for veyron boards
have them enabled [1]. Enable support for them here as well.

[1] https://review.coreboot.org/c/coreboot/+/9719

Signed-off-by: Alper Nebi Yasak <[email protected]>
Reviewed-by: Kever Yang <[email protected]>

Thanks,
- Kever
---

  configs/chromebit_mickey_defconfig  | 1 +
  configs/chromebook_jerry_defconfig  | 1 +
  configs/chromebook_minnie_defconfig | 1 +
  configs/chromebook_speedy_defconfig | 1 +
  4 files changed, 4 insertions(+)

diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index d4302353c5df..253ef99f9939 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MTD=y
  CONFIG_SF_DEFAULT_BUS=2
  CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_PINCTRL=y
  CONFIG_PINCONF=y
  CONFIG_SPL_PINCTRL=y
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 1a54986d089e..3172f04a2648 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MTD=y
  CONFIG_SF_DEFAULT_BUS=2
  CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_PINCTRL=y
  CONFIG_PINCONF=y
  CONFIG_SPL_PINCTRL=y
diff --git a/configs/chromebook_minnie_defconfig 
b/configs/chromebook_minnie_defconfig
index 73ab2f62af5e..25a56f45fe6c 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MTD=y
  CONFIG_SF_DEFAULT_BUS=2
  CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_PINCTRL=y
  CONFIG_PINCONF=y
  CONFIG_SPL_PINCTRL=y
diff --git a/configs/chromebook_speedy_defconfig 
b/configs/chromebook_speedy_defconfig
index 06437aae18d6..ff2a12b25c34 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MTD=y
  CONFIG_SF_DEFAULT_BUS=2
  CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_PINCTRL=y
  CONFIG_PINCONF=y
  CONFIG_SPL_PINCTRL=y

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