> From: Janne Grunau <[email protected]> > Date: Wed, 06 Sep 2023 23:50:34 +0200 > > Apple's M2 Ultra SoC are somewhat similar to the M1 Ultra but needs > a tweaked memory map as the M2 Pro/Max SoCs. USB, NVMe, UART, WDT > and PCIe are working with the existing drivers. > > Signed-off-by: Janne Grunau <[email protected]>
Reviewed-by: Mark Kettenis <[email protected]> > --- > arch/arm/mach-apple/board.c | 183 > ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 183 insertions(+) > > diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c > index d50194811843..47393babbc62 100644 > --- a/arch/arm/mach-apple/board.c > +++ b/arch/arm/mach-apple/board.c > @@ -444,6 +444,187 @@ static struct mm_region t6020_mem_map[] = { > } > }; > > +/* Apple M2 Ultra */ > + > +static struct mm_region t6022_mem_map[] = { > + { > + /* I/O */ > + .virt = 0x280000000, > + .phys = 0x280000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x340000000, > + .phys = 0x340000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x380000000, > + .phys = 0x380000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x580000000, > + .phys = 0x580000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x5a0000000, > + .phys = 0x5a0000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x5c0000000, > + .phys = 0x5c0000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x700000000, > + .phys = 0x700000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0xb00000000, > + .phys = 0xb00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0xf00000000, > + .phys = 0xf00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x1300000000, > + .phys = 0x1300000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2280000000, > + .phys = 0x2280000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2340000000, > + .phys = 0x2340000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2380000000, > + .phys = 0x2380000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2580000000, > + .phys = 0x2580000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x25a0000000, > + .phys = 0x25a0000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x25c0000000, > + .phys = 0x25c0000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2700000000, > + .phys = 0x2700000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2b00000000, > + .phys = 0x2b00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2f00000000, > + .phys = 0x2f00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x3300000000, > + .phys = 0x3300000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* RAM */ > + .virt = 0x10000000000, > + .phys = 0x10000000000, > + .size = 16UL * SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > + PTE_BLOCK_INNER_SHARE > + }, { > + /* Framebuffer */ > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* List terminator */ > + 0, > + } > +}; > + > struct mm_region *mem_map; > > int board_init(void) > @@ -488,6 +669,8 @@ void build_mem_map(void) > else if (of_machine_is_compatible("apple,t6020") || > of_machine_is_compatible("apple,t6021")) > mem_map = t6020_mem_map; > + else if (of_machine_is_compatible("apple,t6022")) > + mem_map = t6022_mem_map; > else > panic("Unsupported SoC\n"); > > > --- > base-commit: c0c08be5468cb26db597932bc69c4eda1129841d > change-id: 20230906-apple_t6022_m2_ultra-9146e34619e6 > > Best regards, > -- > Janne Grunau <[email protected]> > >
