From: Fabio Estevam <feste...@denx.de>
With DM enabled, there is no need for board code to initialize
the FEC interface.
The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
need to enable the RGMII TX clk output.
Also, there is no need for describing the deprecated phy-reset properties
in u-boot.dtsi.
Remove all these uneeded pieces.
Signed-off-by: Fabio Estevam <feste...@denx.de>
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 8 --------
board/freescale/imx8mp_evk/imx8mp_evk.c | 26 +------------------------
2 files changed, 1 insertion(+), 33 deletions(-)
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 43f13a9c22f7..db6bc6a11883 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -150,11 +150,3 @@
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
-
-&fec {
- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <15>;
- phy-reset-post-delay = <100>;
-};
-
-
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index a24b8c1d8608..2c2b8383c8dc 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -20,33 +20,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static void setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Enable RGMII TX clk output */
- setbits_le32(&gpr->gpr[1], BIT(22));
-}
-
-#if CONFIG_IS_ENABLED(NET)
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-#endif
-
int board_init(void)
{
- int ret = 0;
-
- if (IS_ENABLED(CONFIG_FEC_MXC)) {
- setup_fec();
- }
-
- return ret;
+ return 0;
}
int board_late_init(void)
--
2.34.1
