On Tue, Oct 31, 2023 at 12:35:41AM -0500, Samuel Holland wrote: > This is required on CPUs which always operate in CLIC mode, such as the > T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the > trap vector base address held in mtvec is constrained to be aligned on a > 64-byte or larger power-of-two boundary." > > Reported-by: Madushan Nishantha <[email protected]> > Signed-off-by: Samuel Holland <[email protected]> > --- > > arch/riscv/cpu/mtrap.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
