Add evaluation board "adp-ag101" aconfiguration file adp-ag101.h.
Signed-off-by: Macpaul Lin <[email protected]> --- Changes for v1-v4: - code clean up Changes for v5-v6: - Refine the definitions and parameters about CLK, AHB controller, SDRAM controller, Static memory controllers. - Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible. - ftahbc010: - Update include path of ftahbc010. - ftsdmc021: - Update include path of ftsdmc021. - ftsmc020: - Update include path of ftsmc020. - ftwdt010: - Fix WDT define and update include path. - Fix ftwdt010 for hardware reset. - ftpmu010: - Remove duplicate PMU definitions. - Add related configurations. - Fix MAX malloc len and fix saveenv. - clean up. include/configs/adp-ag101.h | 377 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 377 insertions(+), 0 deletions(-) create mode 100644 include/configs/adp-ag101.h diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h new file mode 100644 index 0000000..ec92233 --- /dev/null +++ b/include/configs/adp-ag101.h @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <[email protected]> + * Macpaul Lin, Andes Technology Corporation <[email protected]> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/ag101.h> + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_ADP_AG101 + +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Timer + */ + +/* + * ag101: CONFIG_SYS_HZ: APB_CLK (ag101 original timer clock frequency) + * + * According to the discussion in u-boot mailing list before, + * CONFIG_SYS_HZ at 1000 is mandatory. + */ + +/* + * APB_CLK, AHB_CLK, SYS_CLK are from an old configuration + * in the earlist nds32 bootloader. + * + * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2 + * + * Since the power management (PWM) Timer 4 uses a counter of + * 15625 for 10 ms, so we need it to wrap 100 times + * (total 1562500) to get 1 sec. + * + * #define CONFIG_HZ 1562500 + * 1562500*25=3906250 + */ +#define SYS_CLK CONFIG_SYS_CLK_FREQ +#define AHB_CLK SYS_CLK +#define APB_CLK (SYS_CLK / 2) + +#define CONFIG_SYS_HZ 1000 +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * System Clock + * Suggested frequency lists: + * 16000000 -> 16.000000 MHz + * 18432000 -> 18.432000 MHz + * 22118400 -> 22.118400 MHz + * 83000000 -> 83.000000 MHz + * 33000000 -> 33.000000 MHz + * 36864000 -> 36.864000 MHz + * 48000000 -> 48.000000 MHz CONFIG_ADP_AG101 + * 39062500 -> 39.062500 MHz CONFIG_ADP_AG101P + */ +#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_CLK_FREQ 48000000 +#endif + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/* + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#ifdef CONFIG_ADP_AG101 +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (2*OSC_5MHZ) +#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) +#endif + +/* + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE /* 0x99600000 */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 + +#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_NS16550_CLK (46080000 * 20) / 25 /* AG101 */ +#endif + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Size of malloc() pool + */ +/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * size in bytes reserved for initial data + */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * AHB Controller configuration + */ +#define CONFIG_FTAHBC020S + +#ifdef CONFIG_FTAHBC020S +#include <faraday/ftahbc020s.h> + +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 + +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE)| \ + FTAHBC020S_SLAVE_BSR_SIZE(FTAHBC020S_SLAVE_BSR_SIZE_2G)) +#endif + +/* + * Watchdog + */ +#define CONFIG_FTWDT010_WATCHDOG + +/* + * PMU Power controller configuration + */ +#define CONFIG_PMU +#define CONFIG_FTPMU010_POWER + +#ifdef CONFIG_FTPMU010_POWER +#include <faraday/ftpmu010.h> +#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E +#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR |\+ FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ + FTPMU010_SDRAMHTC_CKE_DCSR | \ + FTPMU010_SDRAMHTC_DQM_DCSR | \ + FTPMU010_SDRAMHTC_SDCLK_DCSR) +#endif + +/* + * SDRAM controller configuration + */ +#define CONFIG_FTSDMC021 + +#ifdef CONFIG_FTSDMC021 +#include <faraday/ftsdmc021.h> + +#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \ + FTSDMC021_TP1_TRCD(1) | \ + FTSDMC021_TP1_TRF(3) | \ + FTSDMC021_TP1_TWR(1) | \ + FTSDMC021_TP1_TCL(2)) + +#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ + FTSDMC021_TP2_INI_REFT(8) | \ + FTSDMC021_TP2_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ + FTSDMC021_CR1_DSZ(3) | \ + FTSDMC021_CR1_MBW(2) | \ + FTSDMC021_CR1_BNKSIZEF(6)) + +#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ + FTSDMC021_CR2_IREF | \ + FTSDMC021_CR2_ISMR) + +#define CONFIG_SYS_FTSDMC021_BANK0_BASECONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE+#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK0_BASE) + +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x0CF00000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x00200000 + +/* + * Static memory controller configuration + */ +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include <faraday/ftsmc020.h> + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifdef CONFIG_ADP_AG101 +/* + * There are 2 bank connected to FTSMC020 on ADP_AG101 + * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM. + * + * Note: + * FLASH on ADP_AG101P (FPGA version of ADP_AG101) is connected to BANK1 + * Just disalbe the other BANK to avoid detection error. + */ + +/* This FTSMC020_BANK1_SDRAM was used in lowlevel_init.S */ +#define FTSMC020_BANK1_SDRAM_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_SDRAM_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(1) | \ + FTSMC020_TPR_CTW(1) | \ + FTSMC020_TPR_ATI(1) | \ + FTSMC020_TPR_AT2(1) | \ + FTSMC020_TPR_WTC(1) | \ + FTSMC020_TPR_AHT(1) | \ + FTSMC020_TPR_TRNA(1)) + +/* + * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH) + * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000) + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) +#endif /* CONFIG_ADP_AG101 */ +#endif /* CONFIG_FTSMC020 */ + +/* + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* support JEDEC */ +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x80400000 + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) +#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x1C0000) +#define CONFIG_ENV_SIZE 8192 +#define CONFIG_ENV_OVERWRITE + +/* relocation parameters */ +#define CONFIG_SYS_RELO_ADDR 0x10000000 + +#endif /* __CONFIG_H */ -- 1.7.3.5 CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. 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