On Wed, Oct 18, 2023 at 3:52 PM Marek Vasut <ma...@denx.de> wrote: > > The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors > in case of an exception. Those high vectors are located at 0xffff0000, which > is where the BootROM exception table is located as well. U-Boot should handle > exceptions on its own using its own exception handling code, which is located > at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump > to low vectors on exception instead, and therefore run the U-Boot exception > handling code. > > Signed-off-by: Marek Vasut <ma...@denx.de>
Applied to u-boot-imx next, thanks.
