The current implementation encounters issues when testing data ranging from 0 to 8 bytes. This was confirmed through testing with both ISSI (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.
Upon investigation, it was observed that utilizing the "SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in STIG mode results in a read failure, leading to a compare test failure. To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. Signed-off-by: Tejas Bhumkar <[email protected]> --- drivers/spi/cadence_qspi.h | 3 +++ drivers/spi/cadence_qspi_apb.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 12825f8911..3b9cee25fa 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -33,6 +33,9 @@ #define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_CLKS_MAX 31 +#define CMD_4BYTE_FAST_READ 0x0C +#define CMD_4BYTE_OCTAL_READ 0x7c + /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d033184aa4..fb90532217 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -469,6 +469,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, else opcode = op->cmd.opcode; + if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr) + opcode = CMD_4BYTE_FAST_READ; + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; /* Set up dummy cycles. */ -- 2.27.0
