On 3/18/24 10:09, mihai.s...@microchip.com wrote: > On 3/7/24 11:10, Alexander Dahl wrote: >> For now adds one new command 'hsmc' with a single subcommand 'decode' >> to read and display the content of the registers of the Static Memory >> Controllers (SMC/HSMC) found in different at91 SoCs. Needed to get a >> better picture on what raw nand core and atmel nand controller driver >> try to set as timings based on ONFI parameters of the connected NAND >> chip. >> >> Tested on SAMA5D2 and SAM9X60 based boards. Example output: >> >> U-Boot> hsmc decode >> >> mck clock rate: 200000000 >> >> SMC_SETUP3: 0x00000002 >> SMC_PULSE3: 0x07040703 >> SMC_CYCLE3: 0x00070007 >> SMC_MODE3: 0x001f0003 >> NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 >> ns) >> NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 >> ns) >> NCS_WR: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 >> ns) >> NWE: setup: 2 (10 ns), pulse: 3 (15 ns), hold: 2 (10 ns), cycle: 7 >> (35 ns) >> Standard read is applied. >> TDF optimization enabled >> TDF cycles: 15 (75 ns) >> Data Bus Width: 8-bit bus >> NWAIT Mode: 0 >> Write operation controlled by NWE signal >> Read operation controlled by NRD signal > > Adding Mihai as he is usually very interested in such debug information and > methods. > > ------------------------------------------------------------------------------------- > > Hi Alexander, > > I tested your work on sama7g54-curiosity board: > > U-Boot> nand info > > Device 0: nand0, sector size 256 KiB > Manufacturer MACRONIX > Model MX30LF4G28AD > Device size 512 MiB > Page size 4096 b > OOB size 256 b > Erase size 262144 b > ecc strength 8 bits > ecc step size 512 b > subpagesize 4096 b > options 0x00004200 > bbt options 0x00028000 > > U-Boot> hsmc decode > > mck clock rate: 200000000 > > HSMC_SETUP3: 0x00000001 > HSMC_PULSE3: 0x07040804 > HSMC_CYCLE3: 0x00070008 > HSMC_TIMINGS3: 0x880402f2 > HSMC_MODE3: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > NCS_WR: setup: 0 (0 ns), pulse: 8 (40 ns), hold: 0 (0 ns), cycle: 8 (40 ns) > NWE: setup: 1 (5 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 8 (40 ns) > TDF optimization enabled > TDF cycles: 15 (75 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > > Best regards, > Mihai Sain
Hello Mihai, If you have any suggestions for improvement, changes, or you are happy with this command, is it useful ? You can provide your Tested-by then if you consider this is useful Eugen
