On Fri, 5 Apr 2024 at 13:45, Neil Armstrong <neil.armstr...@linaro.org> wrote:
>
> Add pinctrl driver for the TLMM block found in the SM8550 SoC.
>
> This driver only handles the gpio and qup1_se7 pinmux, and makes sure
> the pinconf applies on SDC2 pins.
>
> Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 7 ++++
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8550.c | 75
> +++++++++++++++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
Acked-by: Sumit Garg <sumit.g...@linaro.org>
-Sumit
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 2fe63981478..f760bbcdd52 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
> Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
> as well as the associated GPIO driver.
>
> +config PINCTRL_QCOM_SM8550
> + bool "Qualcomm SM8550 GCC"
> + select PINCTRL_QCOM
> + help
> + Say Y here to enable support for pinctrl on the Snapdragon SM8550
> SoC,
> + as well as the associated GPIO driver.
> +
> endmenu
>
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 6d9aca6d7b7..970902e28c8 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
> +obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c
> b/drivers/pinctrl/qcom/pinctrl-sm8550.c
> new file mode 100644
> index 00000000000..d9a8a652111
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Qualcomm sm8550 pinctrl
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + *
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> + {"qup1_se7", 1},
> + {"gpio", 0},
> +};
> +
> +static const char *sm8550_get_function_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sm8550_get_pin_name(struct udevice *dev,
> + unsigned int selector)
> +{
> + static const char *special_pins_names[] = {
> + "ufs_reset",
> + "sdc2_clk",
> + "sdc2_cmd",
> + "sdc2_data",
> + };
> +
> + if (selector >= 210 && selector <= 213)
> + snprintf(pin_name, MAX_PIN_NAME_LEN,
> special_pins_names[selector - 210]);
> + else
> + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +
> + return pin_name;
> +}
> +
> +static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
> + unsigned int selector)
> +{
> + return msm_pinctrl_functions[selector].val;
> +}
> +
> +static struct msm_pinctrl_data sm8550_data = {
> + .pin_data = {
> + .pin_count = 214,
> + .special_pins_start = 210,
> + },
> + .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> + .get_function_name = sm8550_get_function_name,
> + .get_function_mux = sm8550_get_function_mux,
> + .get_pin_name = sm8550_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> + { .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_sm8550) = {
> + .name = "pinctrl_sm8550",
> + .id = UCLASS_NOP,
> + .of_match = msm_pinctrl_ids,
> + .ops = &msm_pinctrl_ops,
> + .bind = msm_pinctrl_bind,
> +};
> +
>
> --
> 2.34.1
>
