This series introduces support for DTR mode for the Cadence QSPI/OSPI
IP. We have been developing it against the SC594/SC598 from ADI, so
there are some limitations specific to our hardware's capabilities.
Ideally this series could be enhanced with features introduced in a
patch series submitted by AMD, but currently no work has been done to
reconcile the two. So this is somewhere between an RFC patch and
a patch series we wish to submit as-is for inclusion.
Beyond the specific support for the QSPI peripheral, this series also
introduces a more general calibration framework as part of the spi
system in order to facilitate integration of calibration support for
other controllers within a consistent approach.
Ian Roberts (11):
mtd: spi-nor: Add calibration hook for high speed SPI
mtd: spi-nor: Octal DTR support for IS25*x
spi: cadence-quadspi: Enable DDR bit for DTR commands
spi: cadence-quadspi: enable opcode extension based on command length
spi: cadence-quadspi: disable automatic write enable
spi: cadence-quadspi: unconditionally disable auto status register
reads
spi: cadence-quadspi: Remove redundant DTR state
spi: cadence-quadspi: Direct mode does not support zero length
addresses
spi: cadence-quadspi: Add support for memory DMA channel transfers
spi: cadence-quadspi: Add DT control of max Read Delay Capture value
spi: cadence-quadspi: Implement high speed calibration
doc/device-tree-bindings/spi/spi-bus.txt | 4 +
doc/device-tree-bindings/spi/spi-cadence.txt | 11 +
drivers/mtd/spi/Kconfig | 12 +
drivers/mtd/spi/spi-nor-core.c | 246 ++++++++
drivers/mtd/spi/spi-nor-ids.c | 6 +-
drivers/spi/cadence_qspi.c | 444 ++++++++++----
drivers/spi/cadence_qspi.h | 105 +++-
drivers/spi/cadence_qspi_apb.c | 572 +++++++++++++++----
drivers/spi/spi-mem.c | 24 +
include/linux/mtd/spi-nor.h | 13 +
include/spi-mem.h | 19 +
11 files changed, 1226 insertions(+), 230 deletions(-)
--
2.43.2
