On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > T30+ SOC have second PLLD - PLLD2 which can be actively used by > DC and act as main DISP1/2 clock parent. > > Tested-by: Agneli <[email protected]> # Toshiba AC100 T20 > Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 > Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565 > Tested-by: Ion Agorria <[email protected]> # HTC One X > Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel <[email protected]> > --- > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > 1 file changed, 6 insertions(+)
Reviewed-by: Thierry Reding <[email protected]>
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