The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block.
Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix
reference clock period configuration.
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.sch...@theobroma-systems.com>
Acked-by: Sean Anderson <sean...@gmail.com>
---
v3: Collect a-b tag
v2: Collect r-b tag
---
drivers/clk/rockchip/clk_rk3588.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3588.c
b/drivers/clk/rockchip/clk_rk3588.c
index 8f33843179b0..4c611a390499 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1569,6 +1569,9 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
case DCLK_DECOM:
rate = rk3588_mmc_get_clk(priv, clk->id);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
rate = OSC_HZ;
@@ -1734,6 +1737,9 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong
rate)
case DCLK_DECOM:
ret = rk3588_mmc_set_clk(priv, clk->id, rate);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
ret = OSC_HZ;
--
2.43.2
