Signed-off-by: Tom Warren <twar...@nvidia.com>
---
arch/arm/cpu/armv7/tegra2/ap20.c | 29 ++++++++++++++++++++++++++++
arch/arm/include/asm/arch-tegra2/clk_rst.h | 6 +++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 075341e..ebbbbd4 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -32,6 +32,32 @@
u32 s_first_boot = 1;
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ reg = readl(&clkrst->crc_pllx_base);
+ if (reg & PLL_ENABLE)
+ return;
+
+ /* Set PLLX_MISC */
+ reg = CPCON; /* CPCON = 0001 */
+ writel(reg, &clkrst->crc_pllx_misc);
+
+ /* Use 12MHz clock here */
+ reg = (PLL_BYPASS | PLL_DIVM);
+ reg |= (1000 << 8); /* DIVN = 0x3E8 */
+ writel(reg, &clkrst->crc_pllx_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, &clkrst->crc_pllx_base);
+
+ reg &= ~PLL_BYPASS;
+ writel(reg, &clkrst->crc_pllx_base);
+}
+
static void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable)
*/
if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h
b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index d67a5d7..bd8ad2c 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -160,8 +160,8 @@ struct clk_rst_ctlr {
#define PLL_DIVP (1 << 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C /* input divider, b4:0 */
-#define SWR_UARTD_RST (1 << 2)
-#define CLK_ENB_UARTD (1 << 2)
+#define SWR_UARTD_RST (1 << 1)
+#define CLK_ENB_UARTD (1 << 1)
#define SWR_UARTA_RST (1 << 6)
#define CLK_ENB_UARTA (1 << 6)
@@ -189,4 +189,6 @@ struct clk_rst_ctlr {
#define CPU0_CLK_STP (1 << 8)
#define CPU1_CLK_STP (1 << 9)
+#define CPCON (1 << 8)
+
#endif /* CLK_RST_H */
--
1.7.4.3
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