On 2024-06-23 06:15, FUKAUMI Naoki wrote: > rk3328-rock-pi-e-v3.dts is identical to rk3328-rock-pi-e.dts in > upstream. only difference between v3.0 and prior ver. is, using > rk3328-sdram-ddr4-666.dtsi instead of rk3328-sdram-ddr3-666.dtsi. > > here is console output from ROCK Pi E v3.0: > > ``` > U-Boot TPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09) > DDR4, 333MHz > BW=32 Col=10 Bk=4 BG=2 CS0 Row=16 CS=1 Die BW=16 Size=2048MB > Trying to boot from BOOTROM > Returning to boot ROM... > > U-Boot SPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09 +0900) > Trying to boot from MMC2 > ``` > > there is an another way which can share same u-boot-rockchip.bin > between v3 and prior, using ddr blob from Rockchip instead of TPL in > U-Boot. is it acceptable?
Maybe it is time to add a small config fragment, rockchip_tpl.config, that enable use of external TPL. e.g. building with: make rock-pi-e-rk3328_defconfig rockchip_tpl.config would expect external TPL and include the external TPL in resulting u-boot-rockchip.bin. > > Signed-off-by: FUKAUMI Naoki <[email protected]> > --- > arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi | 43 + > arch/arm/dts/rk3328-rock-pi-e-v3.dts | 445 ++++ > arch/arm/dts/rk3328.dtsi | 1943 ++++++++++++++++++ > configs/rock-pi-e-v3-rk3328_defconfig | 97 + > 4 files changed, 2528 insertions(+) > create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi > create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts > create mode 100644 arch/arm/dts/rk3328.dtsi > create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig > > diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi > b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi > new file mode 100644 > index 0000000000..d7b22b01d7 > --- /dev/null > +++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2020 Radxa > + */ > + > +#include "rk3328-u-boot.dtsi" > +#include "rk3328-sdram-ddr4-666.dtsi" > + > +/ { > + smbios { > + compatible = "u-boot,sysinfo-smbios"; > + > + smbios { > + system { > + manufacturer = "radxa"; > + product = "rock-pi-e_rk3328"; > + }; > + > + baseboard { > + manufacturer = "radxa"; > + product = "rock-pi-e_rk3328"; > + }; > + > + chassis { > + manufacturer = "radxa"; > + product = "rock-pi-e_rk3328"; > + }; > + }; > + }; > +}; > + > +&u2phy_host { > + phy-supply = <&vcc_host_5v>; > +}; > + > +&vcc_host_5v { > + /delete-property/ regulator-always-on; > + /delete-property/ regulator-boot-on; > +}; > + > +&vcc_sd { > + bootph-pre-ram; > +}; > diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3.dts > b/arch/arm/dts/rk3328-rock-pi-e-v3.dts > new file mode 100644 > index 0000000000..3cda6c627b > --- /dev/null > +++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts > @@ -0,0 +1,445 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * (C) Copyright 2020 Chen-Yu Tsai <[email protected]> > + * > + * Based on ./rk3328-rock64.dts, which is > + * > + * Copyright (c) 2017 PINE64 > + */ > + > +/dts-v1/; > + Here you can just: #include "rk3328-rock-pi-e.dts" and then you should be good. Please see nanopi-m4-2gb, it is same/similar situation, a diff board rev with other DRAM modules. A completely new DT should not be needed. Regards, Jonas [snip] > diff --git a/configs/rock-pi-e-v3-rk3328_defconfig > b/configs/rock-pi-e-v3-rk3328_defconfig > new file mode 100644 > index 0000000000..4c6cc634bd > --- /dev/null > +++ b/configs/rock-pi-e-v3-rk3328_defconfig > @@ -0,0 +1,97 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=24000000 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SPL_GPIO=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_SF_DEFAULT_SPEED=20000000 > +CONFIG_ENV_OFFSET=0x3F8000 > +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3" > +CONFIG_DM_RESET=y > +CONFIG_ROCKCHIP_RK3328=y > +CONFIG_DEBUG_UART_BASE=0xFF130000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SYS_LOAD_ADDR=0x800800 > +CONFIG_DEBUG_UART=y > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_FIT_SIGNATURE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_LEGACY_IMAGE_FORMAT=y > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_MAX_SIZE=0x40000 > +CONFIG_SPL_PAD_TO=0x7f8000 > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +CONFIG_SPL_POWER=y > +CONFIG_SPL_ATF=y > +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > +CONFIG_CMD_BOOTZ=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_TPL_OF_CONTROL=y > +# CONFIG_OF_UPSTREAM is not set > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks > assigned-clock-rates assigned-clock-parents" > +CONFIG_TPL_OF_PLATDATA=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_SYS_MMC_ENV_DEV=1 > +CONFIG_TPL_DM=y > +CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_REGMAP=y > +CONFIG_SPL_REGMAP=y > +CONFIG_TPL_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_SYSCON=y > +CONFIG_TPL_SYSCON=y > +CONFIG_CLK=y > +CONFIG_SPL_CLK=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_PHY_REALTEK=y > +CONFIG_DM_MDIO=y > +CONFIG_DM_ETH_PHY=y > +CONFIG_PHY_GIGE=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_SPL_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_SPL_DM_REGULATOR_FIXED=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_RAM=y > +CONFIG_SPL_RAM=y > +CONFIG_TPL_RAM=y > +CONFIG_DM_RNG=y > +CONFIG_RNG_ROCKCHIP=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550_MEM32=y > +CONFIG_SYSINFO=y > +CONFIG_SYSINFO_SMBIOS=y > +CONFIG_SYSRESET=y > +# CONFIG_TPL_SYSRESET is not set > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC3=y > +CONFIG_USB_DWC3_GENERIC=y > +CONFIG_SPL_TINY_MEMSET=y > +CONFIG_TPL_TINY_MEMSET=y > +CONFIG_ERRNO_STR=y
