Hi, On Mon May 13, 2024 at 10:56 PM CEST, Michael Walle wrote: > Add network support for the V3s which only supports the internal > PHY. Adding support was straight forward. The emac driver just needs > the compatible string and some platform data and the clock driver > needs to know the bits for the clock gating as well as the reset > bits. > > This was tested on a custom board.
Any news here? -michael > > Michael Walle (2): > clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC > net: sun8i_emac: add support for the V3s > > drivers/clk/sunxi/clk_v3s.c | 6 ++++++ > drivers/net/sun8i_emac.c | 7 +++++++ > 2 files changed, 13 insertions(+)
