Hi Neil,
Thank you for the patch.
On ven., juil. 19, 2024 at 15:56, Neil Armstrong <neil.armstr...@linaro.org>
wrote:
> The current flush operation will omit doing a flush/invalidate on
> the first and last bytes if the base address and size are not aligned
> with DMA_MINALIGN.
>
> This causes operation failures Qualcomm platforms.
>
> Take in account the alignment and size of the buffer and also
> flush the previous and last cacheline.
>
> Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpersh...@baylibre.com>
> ---
> drivers/usb/dwc3/io.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
> index 04791d4c9be..1aaf5413c6d 100644
> --- a/drivers/usb/dwc3/io.h
> +++ b/drivers/usb/dwc3/io.h
> @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32
> offset, u32 value)
>
> static inline void dwc3_flush_cache(uintptr_t addr, int length)
> {
> - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
> + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1);
> + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, ARCH_DMA_MINALIGN);
> +
> + flush_dcache_range(start_addr, end_addr);
> }
> #endif /* __DRIVERS_USB_DWC3_IO_H */
>
> --
> 2.34.1
