The TS433 uses both pcie controllers for sata and the 2nd network interface. Set the needed data-lanes in the pcie3 phy and enable the second pcie controller, as well as remove the bifurcation comment.
Tested-by: Uwe Kleine-König <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] [this needs to be replaced, once the patch hits the devicetree-rebasing repo] Signed-off-by: Heiko Stuebner <[email protected]> --- dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts index 07b4f095d76..9bf9c3b65ca 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -78,17 +78,25 @@ }; &pcie30phy { + data-lanes = <1 2>; status = "okay"; }; /* Connected to a JMicron AHCI SATA controller */ &pcie3x1 { - /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; +/* Connected to the 2.5G NIC for the upper network jack */ +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>; -- 2.39.2
