Hi tested full series on bananapi r64
does not break downstream DTS and works with modified upstream dts tested mmc, pci, sata, ethernet, usb Tested-by: Frank Wunderlich <[email protected]> regards Frank > Gesendet: Freitag, 02. August 2024 um 15:48 Uhr > Von: "Christian Marangi" <[email protected]> > An: "Lukasz Majewski" <[email protected]>, "Sean Anderson" <[email protected]>, > "Ryder Lee" <[email protected]>, "Weijie Gao" <[email protected]>, > "Chunfeng Yun" <[email protected]>, "GSS_MTK_Uboot_upstream" > <[email protected]>, "Tom Rini" <[email protected]>, > "Christian Marangi" <[email protected]>, [email protected] > Betreff: [PATCH 8/8] clk: mediatek: mt7622: add missing A1/2SYS clock ID > > Add missing A1/2SYS clock ID just as a reference for OF_UPSTREAM > support. These clocks are not defined and are not usable as current > clock topckgen OPs doesn't support gates. > > These special node won't ever be used by uboot hence just add them for > reference. > > Signed-off-by: Christian Marangi <[email protected]> > --- > include/dt-bindings/clock/mt7622-clk.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/dt-bindings/clock/mt7622-clk.h > b/include/dt-bindings/clock/mt7622-clk.h > index cd11a1c901e..cdbcaef76eb 100644 > --- a/include/dt-bindings/clock/mt7622-clk.h > +++ b/include/dt-bindings/clock/mt7622-clk.h > @@ -117,6 +117,8 @@ > #define CLK_TOP_I2S1_MCK_DIV_PD 104 > #define CLK_TOP_I2S2_MCK_DIV_PD 105 > #define CLK_TOP_I2S3_MCK_DIV_PD 106 > +#define CLK_TOP_A1SYS_HP_DIV_PD 107 > +#define CLK_TOP_A2SYS_HP_DIV_PD 108 > > /* INFRACFG */ > > -- > 2.45.2 > >
