On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote: > From: Timur Tabi <ti...@freescale.com> > > SerDes PLL bandwidth default setting is incorrect when no lanes are > configured as PCI Express. > > Signed-off-by: Timur Tabi <ti...@freescale.com> > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> > --- > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 ++ > arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 48 +++++++++++++++++++++++++ > arch/powerpc/include/asm/config_mpc85xx.h | 1 + > 3 files changed, 52 insertions(+), 0 deletions(-)
applied to 85xx - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot