This series picks up the work from Volodymyr Babchuk (https://lore.kernel.org/u-boot/[email protected]). clk and pinctrl drivers are adjusted to work similarly to existing qcom drivers. I could only test this using android boot chainloading.
Fixed wrong register values in sm8150_clks, alphabetic ordering and added GCC_SDCC2_APPS_CLK rate setting. Thanks for all the help again! Signed-off-by: Julius Lehmann <[email protected]> --- Changes in v3: - fix: config: alphabetic ordering in Kconfig and Makefile - fix: clk: qcom: sm8150 if expression in clk_enable now correct - add: clk: qcom: sm8150 initialize GCC_SDCC2_APPS_CLK (similar to other clock drivers) - fix: clk: qcom: sm8150 GCC_UFS_* clock registers were wrong, copied correct ones over from Linux - Link to v2: https://lore.kernel.org/r/[email protected] Changes in v2: - fix: clk: qcom: sm8150 command registers for phy_aux_clk (usb) - refactor: pinctrl: qcom: sm8150 use special_pin_start and special_pins_data - Link to v1: https://lore.kernel.org/r/[email protected] --- Julius Lehmann (3): clk: qcom: add driver for SM8150 SoC pinctrl: qcom: add driver for SM8150 SoC config: qcom: add sm8150 to qcom_defconfig configs/qcom_defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm8150.c | 319 ++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 156 +++++++++++++++++ 7 files changed, 496 insertions(+) --- base-commit: 78d898eec080b02059c8dc09318b8761044fea85 change-id: 20240910-sm8150-patches-559cc2475ded Best regards, -- Julius Lehmann <[email protected]>
