Hi Marek,
On 9/25/24 19:04, Marek Vasut wrote:
On 6/19/24 8:35 AM, Patrice CHOTARD wrote:
On 6/19/24 00:57, Marek Vasut wrote:
Update the TAMP_SMCR BKP..PROT fields to put first 10 registers
into protection zone 1 and next 5 into zone 2. This fixes use of
boot counter which is often in zone 3 and has to be updated from
Linux, which runs in NS.
Fixes: 73f7fc944cf6 ("ARM: stm32: Initialize TAMP_SMCR BKP..PROT
fields on STM32MP15xx")
Signed-off-by: Marek Vasut <[email protected]>
---
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
index f096fe538d8..ca202bec8ee 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
@@ -148,8 +148,8 @@ static void security_init(void)
*/
clrsetbits_le32(TAMP_SMCR,
TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
- FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
- FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
+ FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) |
+ FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F));
/* GPIOZ: deactivate the security */
writel(BIT(0), RCC_MP_AHB5ENSETR);
Reviewed-by: Patrice Chotard <[email protected]>
I hope this bugfix will make it into 2024.10 , can you prepare a
bugfix PR for 2024.10 ?
Thanks for reminder, I miss it.
And sorry for the delay, because a pull request was planned by Patrice
after with summer holiday....
but unfortunately it can't do it now (he is out of the office for a few
weeks after a small incident)
so I will push a PR this week with your 2 bugfix patches.
Regards
Patrick
