To support JH7110 based boards besides v1.3B,
add a common dtsi and add common code to it.
Signed-off-by: Hal Feng <hal.f...@starfivetech.com>
---
arch/riscv/dts/jh7110-common-u-boot.dtsi | 150 ++++++++++++++++++
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 146 +----------------
2 files changed, 151 insertions(+), 145 deletions(-)
create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi
b/arch/riscv/dts/jh7110-common-u-boot.dtsi
new file mode 100644
index 0000000000..cfd3c04aec
--- /dev/null
+++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootph-pre-ram;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ bootph-pre-ram;
+ };
+
+ config {
+ bootph-pre-ram;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ bootph-pre-ram;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+ reg-offset = <0>;
+ current-speed = <115200>;
+ clock-frequency = <24000000>;
+};
+
+&mmc0 {
+ bootph-pre-ram;
+ compatible = "snps,dw-mshc";
+};
+
+&mmc1 {
+ bootph-pre-ram;
+ compatible = "snps,dw-mshc";
+};
+
+&qspi {
+ bootph-pre-ram;
+ spi-max-frequency = <250000000>;
+
+ flash@0 {
+ bootph-pre-ram;
+ /delete-property/ cdns,read-delay;
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&syscrg {
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+ <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+ <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF>;
+ assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
+&aoncrg {
+ assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
+ assigned-clock-parents = <&osc>;
+ assigned-clock-rates = <0>;
+};
+
+&sysgpio {
+ bootph-pre-ram;
+};
+
+&mmc0_pins {
+ bootph-pre-ram;
+ rst-pins {
+ bootph-pre-ram;
+ };
+};
+
+&mmc1_pins {
+ bootph-pre-ram;
+ clk-pins {
+ bootph-pre-ram;
+ };
+
+ mmc-pins {
+ bootph-pre-ram;
+ };
+};
+
+&i2c5_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+&i2c5 {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&binman {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x40400000>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+
+ spl-img {
+ filename = "spl/u-boot-spl.bin.normal.out";
+
+ mkimage {
+ args = "-T sfspl";
+
+ u-boot-spl {
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
index 2b063414e5..f4807957ae 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -3,48 +3,7 @@
* Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- aliases {
- spi0 = &qspi;
- };
-
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 = &qspi;
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x100000>;
- };
-
- memory@40000000 {
- bootph-pre-ram;
- };
-};
-
-&uart0 {
- bootph-pre-ram;
- reg-offset = <0>;
- current-speed = <115200>;
- clock-frequency = <24000000>;
-};
-
-&mmc0 {
- bootph-pre-ram;
- compatible = "snps,dw-mshc";
-};
-
-&mmc1 {
- bootph-pre-ram;
- compatible = "snps,dw-mshc";
-};
+#include "jh7110-common-u-boot.dtsi"
&phy0 {
rx-internal-delay-ps = <1900>;
@@ -53,106 +12,3 @@
&phy1 {
rx-internal-delay-ps = <0>;
};
-
-&qspi {
- bootph-pre-ram;
- spi-max-frequency = <250000000>;
-
- flash@0 {
- bootph-pre-ram;
- /delete-property/ cdns,read-delay;
- spi-max-frequency = <100000000>;
- };
-};
-
-&syscrg {
- assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
- <&syscrg JH7110_SYSCLK_BUS_ROOT>,
- <&syscrg JH7110_SYSCLK_PERH_ROOT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
- assigned-clock-rates = <0>, <0>, <0>, <0>;
-};
-
-&aoncrg {
- assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
- assigned-clock-parents = <&osc>;
- assigned-clock-rates = <0>;
-};
-
-&sysgpio {
- bootph-pre-ram;
-};
-
-&mmc0_pins {
- bootph-pre-ram;
- rst-pins {
- bootph-pre-ram;
- };
-};
-
-&mmc1_pins {
- bootph-pre-ram;
- clk-pins {
- bootph-pre-ram;
- };
-
- mmc-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5_pins {
- bootph-pre-ram;
- i2c-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5 {
- bootph-pre-ram;
- eeprom@50 {
- bootph-pre-ram;
- compatible = "atmel,24c04";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
-
-&binman {
- itb {
- fit {
- images {
- fdt-1 {
- description = "NAME";
- load = <0x40400000>;
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- conf-1 {
- fdt = "fdt-1";
- };
- };
- };
- };
-
- spl-img {
- filename = "spl/u-boot-spl.bin.normal.out";
-
- mkimage {
- args = "-T sfspl";
-
- u-boot-spl {
- };
- };
- };
-};
--
2.43.2
