Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.
Signed-off-by: Thomas Bonnefille <thomas.bonnefi...@bootlin.com>
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
arch/riscv/dts/sg2002.dtsi | 34 +++++++++++++++++++++++
3 files changed, 80 insertions(+)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index
17cda483e128996bb944f5a2b9b7676d32e45ae5..0848cded398d45955dcc17b339dc1869829c6467
100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
+dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/sg2002-licheerv-nano-b.dts
b/arch/riscv/dts/sg2002-licheerv-nano-b.dts
new file mode 100644
index
0000000000000000000000000000000000000000..9871a75836c04a0b0943dc44c6a1090c90752dbd
--- /dev/null
+++ b/arch/riscv/dts/sg2002-licheerv-nano-b.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefi...@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include "sg2002.dtsi"
+
+/ {
+ model = "LicheeRV Nano B";
+ compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano",
"sophgo,sg2002";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/sg2002.dtsi b/arch/riscv/dts/sg2002.dtsi
new file mode 100644
index
0000000000000000000000000000000000000000..0f97000fa8beaaa10a08d03211f7c4a0c2f6e001
--- /dev/null
+++ b/arch/riscv/dts/sg2002.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefi...@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,sg2002";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&plic {
+ compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-plic",
"thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-clint",
"thead,c900-clint";
+};
+
+&clk {
+ compatible = "sophgo,sg2002-clk", "sophgo,cv1800-clk";
+};
+
+&sdhci0 {
+ compatible = "sophgo,sg2002-dwcmshc", "sophgo,cv1800b-dwcmshc";
+};
--
2.47.0
