Hi, Neha,
On 22/10/24 14:52, Neha Malcom Francis wrote:
Hi Santhosh
On 21/10/24 10:10, Santhosh Kumar K wrote:
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <s...@ti.com>
Signed-off-by: Neha Malcom Francis <n-fran...@ti.com>
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ++++---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12 ++++++++----
arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++++++++++++++++--------
3 files changed, 28 insertions(+), 15 deletions(-)
Thank you for this series. Maybe I missed something, but why is this DT
patch at the very end of the series? Doesn't it make sense to include it
before the patches triggering inline ECC i.e. patch 7/8?
True, will change the order in next version.
Regards,
Santhosh.
Sanity tested inline ECC on j784s4 and j721s2 and all looks good [1].
Tested-by: Neha Malcom Francis <n-fran...@ti.com>
[1] https://gist.github.com/nehamalcom/66f1a2ef5288a94eebabe97708b5a277
