Re: [PATCH 2/2] rockchip: sdram: Fix reserve of 2 MiB at start of DRAM

[Kever Yang]

Hi Jonas,

    This patch has the same main change with Heiko's patch.

https://patchwork.ozlabs.org/project/uboot/patch/20241121142731.1202209-9-he...@sntech.de/


Thanks,
- Kever
On 2025/1/24 06:02, Jonas Karlman wrote:

Normally 2 MiB at the beginning of DRAM is reserved for TF-A use.
However, this only works as intended when DRAM starts at 0x0.

When DRAM starts at e.g. 0x40000000 this reservation never happens, and
U-Boot or Linux may try to read/write into secure memory.

Fix this by taking CFG_SYS_SDRAM_BASE into consideration when reserving
2 MiB at start of DRAM.

Also change to use SZ_2M and SZ_32M for consistency.

Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
  arch/arm/mach-rockchip/sdram.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 3d3fc327234f..caca6f917305 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -182,9 +182,9 @@ static int rockchip_dram_init_banksize(void)
                 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
                 * have it, so force this space as reserved.
                 */
-               if (start_addr < SZ_2M) {
-                       size -= SZ_2M - start_addr;
-                       start_addr = SZ_2M;
+               if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
+                       size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
+                       start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
                }

/*

@@ -302,8 +302,8 @@ int dram_init_banksize(void)
        debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
              ret);

- /* Reserve 0x200000 for ATF bl31 */

-       gd->bd->bi_dram[0].start = 0x200000;
+       /* Reserve 2M for ATF bl31 */
+       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
        gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;

/* Add usable memory beyond the blob of space for peripheral near 4GB */

@@ -332,7 +332,7 @@ int dram_init_banksize(void)
                gd->bd->bi_dram[0].size = 0x8400000;
                /* Reserve 32M for OPTEE with TA */
                gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
-                                       + gd->bd->bi_dram[0].size + 0x2000000;
+                                       + gd->bd->bi_dram[0].size + SZ_32M;
                gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
        }
  #else