Dear Graeme Russ, In message <[email protected]> you wrote: > > > No, not at all. And I already answered this. For example on PPC, just > > reading the timebase would be perfectly sufficient, and simpler and > > more reliable than the current interrupt based approach. > > I assume by 'timebase' you mean the 64-bit tick counter. If so, that is
By timebase I mean the timebase register, implemented as two 32 bit registers tbu and tbl, holding the upper and the lower 32 bits of the free-running 64 bit counter, respective. > _exactly_ what I am suggesting we do (and what does already happen on ARM). I don't think so. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] "...this does not mean that some of us should not want, in a rather dispassionate sort of way, to put a bullet through csh's head." - Larry Wall in <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
