From: Prasad Kummari <[email protected]> When SPI_STACKED_PARALLEL is enabled, the chip selects properties are read from the device tree using the reg property and stored in the plat->cs[] array. However, the function dev_read_u32_array() returns zero, causing the execution to enter the else block, print an error message, and return. As a result, the spi-max-frequency property is not read from the device tree, resulting in the use of the default frequency SPI_DEFAULT_SPEED_HZ (100,000). This leads to a lower spi->speed, reducing QSPI DMA read performance.
To address this issue, an additional condition has been added to check the return value of reg. If it is nonzero, the function prints an error message and returns. Otherwise, it proceeds to read the spi-max-frequency property from the device tree. Signed-off-by: Prasad Kummari <[email protected]> Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> --- drivers/spi/spi-uclass.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d6049753740..a7783b6b6dd 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -523,8 +523,10 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { dev_read_u32(dev, "reg", &plat->cs[0]); } else { - dev_err(dev, "has no valid 'reg' property (%d)\n", ret); - return ret; + if (ret) { + dev_err(dev, "has no valid 'reg' property (%d)\n", ret); + return ret; + } } #else plat->cs[0] = dev_read_u32_default(dev, "reg", -1); -- 2.25.1
