On Jun 6, 2011, at 8:42 PM, York Sun wrote:
> We used to have fixed parameters for soldered DDR chips. This patch introduces
> CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR
> chip datasheet, implemneted in board-specific files or header files.
>
> Signed-off-by: York Sun <york...@freescale.com>
> ---
> README | 6 ++++++
> arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++-
> arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 13 +++++++++++--
> arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 9 +++++++++
> arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++++++++++
> 5 files changed, 41 insertions(+), 3 deletions(-)
>
> diff --git a/README b/README
> index 8bb9c8d..c1ddfd0 100644
> --- a/README
> +++ b/README
> @@ -2930,6 +2930,12 @@ Low Level (hardware related) configuration options:
> one, specify here. Note that the value must resolve
> to something your driver can deal with.
>
> +- CONFIG_SYS_DDR_RAW_TIMING
> + Get DDR timing information from other than SPD. Common with
> + soldered DDR chips onboard without SPD. DDR raw timing
> + parameters are extracted from datasheet and hard-coded into
> + header files or board specific files.
> +
How is this not just !CONFIG_SPD ?
> - CONFIG_SYS_83XX_DDR_USES_CS0
> Only for 83xx systems. If specified, then DDR should
> be configured using CS0 and CS1 instead of CS2 and CS3.
>
>
> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> index 1e866fe..220fdc4 100644
> --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> @@ -14,6 +14,7 @@
>
> #include "common_timing_params.h"
>
> +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
> /*
> * Bind the main DDR setup driver's generic names
> * to this specific DDR technology.
> @@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
> {
> return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
> }
> +#endif
>
> /*
> * Data Structures
> @@ -80,4 +82,11 @@ extern void check_interleaving_options(fsl_ddr_info_t
> *pinfo);
> extern unsigned int mclk_to_picos(unsigned int mclk);
> extern unsigned int get_memory_clk_period_ps(void);
> extern unsigned int picos_to_mclk(unsigned int picos);
> +
> +/* board specific function */
> +#ifdef CONFIG_SYS_DDR_RAW_TIMING
> +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
> + unsigned int controller_number,
> + unsigned int dimm_number);
where is this code?
> +#endif /* CONFIG_SYS_DDR_RAW_TIMING */
> #endif
> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> index 62a73dd..3c49fa9 100644
> --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> @@ -325,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
> start_step,
>
> switch (start_step) {
> case STEP_GET_SPD:
> +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
> /* STEP 1: Gather all DIMM SPD data */
> for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
> fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
> @@ -356,6 +357,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
> start_step,
> }
> }
>
> +#else
> + case STEP_COMPUTE_DIMM_PARMS:
> + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
> + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
> + dimm_params_t *pdimm =
> + &(pinfo->dimm_params[i][j]);
> + fsl_ddr_get_dimm_params(pdimm, i, j);
> + }
> + }
> + debug("Filling dimm parameters from board specific file\n");
> +#endif
> case STEP_COMPUTE_COMMON_PARMS:
> /*
> * STEP 3: Compute a common set of timing parameters
> --
> 1.7.0.4
>
>
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