On Sat, Apr 26, 2025 at 04:56:57PM +0000, Yao Zi wrote: > [EXTERNAL MAIL] > > Introduce the SoC-specific code and corresponding Kconfig entries for > TH1520 SoC. Following features are implemented for TH1520, > > - Cache enable/disable through customized CSR > - Invalidation of customized PMP entries > - DRAM driver probing for SPL > > Signed-off-by: Yao Zi <[email protected]> > --- > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/th1520/Kconfig | 21 ++++++++++++++++ > arch/riscv/cpu/th1520/Makefile | 8 ++++++ > arch/riscv/cpu/th1520/cache.c | 32 ++++++++++++++++++++++++ > arch/riscv/cpu/th1520/cpu.c | 21 ++++++++++++++++ > arch/riscv/cpu/th1520/dram.c | 21 ++++++++++++++++ > arch/riscv/cpu/th1520/spl.c | 31 +++++++++++++++++++++++ > arch/riscv/include/asm/arch-th1520/cpu.h | 9 +++++++ > arch/riscv/include/asm/arch-th1520/spl.h | 10 ++++++++ > 9 files changed, 154 insertions(+) > create mode 100644 arch/riscv/cpu/th1520/Kconfig > create mode 100644 arch/riscv/cpu/th1520/Makefile > create mode 100644 arch/riscv/cpu/th1520/cache.c > create mode 100644 arch/riscv/cpu/th1520/cpu.c > create mode 100644 arch/riscv/cpu/th1520/dram.c > create mode 100644 arch/riscv/cpu/th1520/spl.c > create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h > create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
