Re: [PATCH 3/6] pci: pcie_dw_qcom: Use dw_pcie_link_set_max_link_width()

[Neil Armstrong]

On 17/06/2025 10:16, Marek Vasut wrote:

Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality.

Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---
Cc: Casey Connolly <casey.conno...@linaro.org>
Cc: Christian Marangi <ansuels...@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Cc: Jiaxun Yang <jiaxun.y...@flygoat.com>
Cc: John Crispin <j...@phrozen.org>
Cc: Kever Yang <kever.y...@rock-chips.com>
Cc: Neil Armstrong <neil.armstr...@linaro.org>
Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
Cc: Philipp Tomsich <philipp.toms...@vrull.eu>
Cc: Siddharth Vadapalli <s-vadapa...@ti.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Sumit Garg <sumit.g...@kernel.org>
Cc: Tom Rini <tr...@konsulko.com>
Cc: u-boot-amlo...@groups.io
Cc: u-boot-q...@groups.io
Cc: u-boot@lists.denx.de
---
  drivers/pci/pcie_dw_qcom.c | 19 +------------------
  1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c
index 39b4cd4efe2..978754e8472 100644
--- a/drivers/pci/pcie_dw_qcom.c
+++ b/drivers/pci/pcie_dw_qcom.c
@@ -213,17 +213,6 @@ static void qcom_pcie_clear_hpc(struct qcom_pcie *priv)
        dw_pcie_dbi_write_enable(&priv->dw, false);
  }

-static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes)

-{
-       u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
-       u32 val;
-
-       val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
-       val &= ~PCI_EXP_LNKCAP_MLW;
-       val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes);
-       writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
-}
-
  static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv)
  {
        /* iommu map structure */
@@ -299,15 +288,9 @@ static void qcom_pcie_configure(struct qcom_pcie *priv)
        val &= ~PORT_LINK_FAST_LINK_MODE;
        val |= PORT_LINK_DLL_LINK_EN;
        val &= ~PORT_LINK_MODE_MASK;
-       val |= PORT_LINK_MODE_2_LANES;
        writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);

- val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

-       val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
-       val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
-       writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
-
-       qcom_pcie_set_lanes(priv, 2);
+       dw_pcie_link_set_max_link_width(&priv->dw, 2);

dw_pcie_dbi_write_enable(&priv->dw, false);

  }

I'll need to validate it on HW, but it looks fine:
Reviewed-by: Neil Armstrong <neil.armstr...@linaro.org>