From: Magnus Damm <[email protected]> Break out SoC specific code from the GR-Peach board and put it into the board/renesas/common directory so it can be easily shared between the GR-Peach and Genmai boards.
Signed-off-by: Magnus Damm <[email protected]> --- board/renesas/common/Makefile | 6 + board/renesas/common/rza1-common.c | 27 +++++++ board/renesas/common/rza1-lowlevel_init.S | 106 +++++++++++++++++++++++++++++ board/renesas/grpeach/Makefile | 1 board/renesas/grpeach/grpeach.c | 22 ------ board/renesas/grpeach/lowlevel_init.S | 106 ----------------------------- 6 files changed, 139 insertions(+), 129 deletions(-) diff -urN u-boot-v2025.07-rc5/board/renesas/common/Makefile u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/Makefile --- u-boot-v2025.07-rc5/board/renesas/common/Makefile 2025-06-06 19:15:44.898179467 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/Makefile 2025-06-28 05:35:38.636922889 +0900 @@ -45,3 +45,9 @@ endif endif + +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif + diff -urN u-boot-v2025.07-rc5/board/renesas/common/rza1-common.c u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/rza1-common.c --- u-boot-v2025.07-rc5/board/renesas/common/rza1-common.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/rza1-common.c 2025-06-28 05:35:59.180039448 +0900 @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff -urN u-boot-v2025.07-rc5/board/renesas/common/rza1-lowlevel_init.S u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/rza1-lowlevel_init.S --- u-boot-v2025.07-rc5/board/renesas/common/rza1-lowlevel_init.S 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/common/rza1-lowlevel_init.S 2025-06-28 05:35:38.636922889 +0900 @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) 2017 Chris Brandt + */ +#include <config.h> +#include <asm/macro.h> + +/* Watchdog Registers */ +#define RZA1_WDT_BASE 0xFCFE0000 +#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ +#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ +#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ + +/* Standby controller registers (chapter 55) */ +#define RZA1_STBCR_BASE 0xFCFE0020 +#define STBCR1 (RZA1_STBCR_BASE + 0x00) +#define STBCR2 (RZA1_STBCR_BASE + 0x04) +#define STBCR3 (RZA1_STBCR_BASE + 0x400) +#define STBCR4 (RZA1_STBCR_BASE + 0x404) +#define STBCR5 (RZA1_STBCR_BASE + 0x408) +#define STBCR6 (RZA1_STBCR_BASE + 0x40c) +#define STBCR7 (RZA1_STBCR_BASE + 0x410) +#define STBCR8 (RZA1_STBCR_BASE + 0x414) +#define STBCR9 (RZA1_STBCR_BASE + 0x418) +#define STBCR10 (RZA1_STBCR_BASE + 0x41c) +#define STBCR11 (RZA1_STBCR_BASE + 0x420) +#define STBCR12 (RZA1_STBCR_BASE + 0x424) +#define STBCR13 (RZA1_STBCR_BASE + 0x450) + +/* Clock Registers */ +#define RZA1_FRQCR_BASE 0xFCFE0010 +#define FRQCR (RZA1_FRQCR_BASE + 0x00) +#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) + +#define SYSCR1 0xFCFE0400 /* System control register 1 */ +#define SYSCR2 0xFCFE0404 /* System control register 2 */ +#define SYSCR3 0xFCFE0408 /* System control register 3 */ + +/* Disable WDT */ +#define WTCSR_D 0xA518 +#define WTCNT_D 0x5A00 + +/* Enable all peripheral clocks */ +#define STBCR3_D 0x00000000 +#define STBCR4_D 0x00000000 +#define STBCR5_D 0x00000000 +#define STBCR6_D 0x00000000 +#define STBCR7_D 0x00000024 +#define STBCR8_D 0x00000005 +#define STBCR9_D 0x00000000 +#define STBCR10_D 0x00000000 +#define STBCR11_D 0x000000c0 +#define STBCR12_D 0x000000f0 + +/* + * Set all system clocks to full speed. + * On reset, the CPU will be running at 1/2 speed. + * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges + */ +#define FRQCR_D 0x0035 +#define FRQCR2_D 0x0001 + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* PL310 init */ + write32 0x3fffff80, 0x00000001 + + /* Disable WDT */ + write16 WTCSR, WTCSR_D + write16 WTCNT, WTCNT_D + + /* Set clocks */ + write16 FRQCR, FRQCR_D + write16 FRQCR2, FRQCR2_D + + /* Enable all peripherals(Standby Control) */ + write8 STBCR3, STBCR3_D + write8 STBCR4, STBCR4_D + write8 STBCR5, STBCR5_D + write8 STBCR6, STBCR6_D + write8 STBCR7, STBCR7_D + write8 STBCR8, STBCR8_D + write8 STBCR9, STBCR9_D + write8 STBCR10, STBCR10_D + write8 STBCR11, STBCR11_D + write8 STBCR12, STBCR12_D + + /* For serial booting, enable read ahead caching to speed things up */ +#define DRCR_0 0x3FEFA00C + write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ + + /* Enable all internal RAM */ + write8 SYSCR1, 0xFF + write8 SYSCR2, 0xFF + write8 SYSCR3, 0xFF + + nop + /* back to arch calling code */ + mov pc, lr + + .align 4 diff -urN u-boot-v2025.07-rc5/board/renesas/grpeach/grpeach.c u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/grpeach.c --- u-boot-v2025.07-rc5/board/renesas/grpeach/grpeach.c 2024-05-18 16:38:52.910534943 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/grpeach.c 2025-06-28 05:44:36.525976339 +0900 @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff -urN u-boot-v2025.07-rc5/board/renesas/grpeach/lowlevel_init.S u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/lowlevel_init.S --- u-boot-v2025.07-rc5/board/renesas/grpeach/lowlevel_init.S 2024-05-18 16:38:52.910534943 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/lowlevel_init.S 1970-01-01 09:00:00.000000000 +0900 @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Renesas Electronics - * Copyright (C) 2017 Chris Brandt - */ -#include <config.h> -#include <asm/macro.h> - -/* Watchdog Registers */ -#define RZA1_WDT_BASE 0xFCFE0000 -#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ -#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ -#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ - -/* Standby controller registers (chapter 55) */ -#define RZA1_STBCR_BASE 0xFCFE0020 -#define STBCR1 (RZA1_STBCR_BASE + 0x00) -#define STBCR2 (RZA1_STBCR_BASE + 0x04) -#define STBCR3 (RZA1_STBCR_BASE + 0x400) -#define STBCR4 (RZA1_STBCR_BASE + 0x404) -#define STBCR5 (RZA1_STBCR_BASE + 0x408) -#define STBCR6 (RZA1_STBCR_BASE + 0x40c) -#define STBCR7 (RZA1_STBCR_BASE + 0x410) -#define STBCR8 (RZA1_STBCR_BASE + 0x414) -#define STBCR9 (RZA1_STBCR_BASE + 0x418) -#define STBCR10 (RZA1_STBCR_BASE + 0x41c) -#define STBCR11 (RZA1_STBCR_BASE + 0x420) -#define STBCR12 (RZA1_STBCR_BASE + 0x424) -#define STBCR13 (RZA1_STBCR_BASE + 0x450) - -/* Clock Registers */ -#define RZA1_FRQCR_BASE 0xFCFE0010 -#define FRQCR (RZA1_FRQCR_BASE + 0x00) -#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) - -#define SYSCR1 0xFCFE0400 /* System control register 1 */ -#define SYSCR2 0xFCFE0404 /* System control register 2 */ -#define SYSCR3 0xFCFE0408 /* System control register 3 */ - -/* Disable WDT */ -#define WTCSR_D 0xA518 -#define WTCNT_D 0x5A00 - -/* Enable all peripheral clocks */ -#define STBCR3_D 0x00000000 -#define STBCR4_D 0x00000000 -#define STBCR5_D 0x00000000 -#define STBCR6_D 0x00000000 -#define STBCR7_D 0x00000024 -#define STBCR8_D 0x00000005 -#define STBCR9_D 0x00000000 -#define STBCR10_D 0x00000000 -#define STBCR11_D 0x000000c0 -#define STBCR12_D 0x000000f0 - -/* - * Set all system clocks to full speed. - * On reset, the CPU will be running at 1/2 speed. - * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges - */ -#define FRQCR_D 0x0035 -#define FRQCR2_D 0x0001 - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* PL310 init */ - write32 0x3fffff80, 0x00000001 - - /* Disable WDT */ - write16 WTCSR, WTCSR_D - write16 WTCNT, WTCNT_D - - /* Set clocks */ - write16 FRQCR, FRQCR_D - write16 FRQCR2, FRQCR2_D - - /* Enable all peripherals(Standby Control) */ - write8 STBCR3, STBCR3_D - write8 STBCR4, STBCR4_D - write8 STBCR5, STBCR5_D - write8 STBCR6, STBCR6_D - write8 STBCR7, STBCR7_D - write8 STBCR8, STBCR8_D - write8 STBCR9, STBCR9_D - write8 STBCR10, STBCR10_D - write8 STBCR11, STBCR11_D - write8 STBCR12, STBCR12_D - - /* For serial booting, enable read ahead caching to speed things up */ -#define DRCR_0 0x3FEFA00C - write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ - - /* Enable all internal RAM */ - write8 SYSCR1, 0xFF - write8 SYSCR2, 0xFF - write8 SYSCR3, 0xFF - - nop - /* back to arch calling code */ - mov pc, lr - - .align 4 diff -urN u-boot-v2025.07-rc5/board/renesas/grpeach/Makefile u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/Makefile --- u-boot-v2025.07-rc5/board/renesas/grpeach/Makefile 2024-05-18 16:38:52.910534943 +0900 +++ u-boot-v2025.07-rc5-renesas-common-a1-v2/board/renesas/grpeach/Makefile 2025-06-28 05:35:38.636922889 +0900 @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o
