From: Magnus Damm <d...@opensource.se>
Here's a hack that adds SDRAM setup code to the r7s72100 Genmai board.
Might be useful in case someone wants to boot Linux on the Genmai board.
Before merge a few unclear points remain:
- How to make best use of the on-chip SDRAM?
The U-Boot DTS currently has a node for the 10 MiB at 0x20000000
Also used by CONFIG_CUSTOM_SYS_INIT_SP_ADDR in renesas_rza1.config
- CONFIG_NR_DRAM_BANKS is set to 3 but lmb_dump_all shows 2 (see below).
- It would be nicer to use DT for the pinmux instead of RZA1_PINMUX()
Serial Console Log:
U-Boot 2025.07 (Jul 11 2025 - 16:12:56 +0900)
Model: Genmai
DRAM: 10 MiB (total 138 MiB)
Core: 30 devices, 12 uclasses, devicetree: separate
Loading Environment from MTD... *** Warning - get_mtd_device_nm() failed, usingt
In: serial@e8008000
Out: serial@e8008000
Err: serial@e8008000
Net:
Warning: ethernet@e8203000 (eth0) using random MAC address - 9e:a3:2c:7a:0f:3a
eth0: ethernet@e8203000
=> bd
boot_params = 0x20000100
DRAM bank = 0x00000000
-> start = 0x08000000
-> size = 0x04000000
DRAM bank = 0x00000001
-> start = 0x0c000000
-> size = 0x04000000
DRAM bank = 0x00000002
-> start = 0x20000000
-> size = 0x00a00000
flashstart = 0x00000000
flashsize = 0x00000000
flashoffset = 0x00000000
baudrate = 115200 bps
relocaddr = 0x209b5000
reloc off = 0x209b5000
Build = 32-bit
current eth = ethernet@e8203000
ethaddr = 9e:a3:2c:7a:0f:3a
IP addr = <NULL>
fdt_blob = 0x208afac0
lmb_dump_all:
memory.count = 0x2
memory[0] [0x8000000-0xfffffff], 0x8000000 bytes, flags: none
memory[1] [0x20000000-0x209fffff], 0xa00000 bytes, flags: none
reserved.count = 0x0
devicetree = separate
arch_number = 0x00000000
TLB addr = 0x209f0000
irq_sp = 0x208afab0
sp start = 0x208afaa0
Early malloc usage: 3bc / 400
=>
Not-yet-Signed-off-by: Magnus Damm <d...@opensource.se>
---
Written on top of u-boot master 6bb0679377abb01a82db1ce69b5bf1d40aa02ace
also 5f520875bdf reverted to work around build issues
board/renesas/genmai/genmai.c | 112 +++++++++++++++++++---
configs/genmai_defconfig | 5
configs/grpeach_defconfig | 2
configs/renesas_rza1.config | 1
dts/upstream/src/arm/renesas/r7s72100-genmai.dts | 22 +++-
5 files changed, 124 insertions(+), 18 deletions(-)
--- 0001/board/renesas/genmai/genmai.c
+++ work/board/renesas/genmai/genmai.c 2025-07-11 16:11:32.621707802 +0900
@@ -12,6 +12,16 @@
#define CS0WCR (RZA1_BCR_BASE + 0x28)
#define CS1BCR (RZA1_BCR_BASE + 0x08)
#define CS1WCR (RZA1_BCR_BASE + 0x2c)
+#define CS2BCR (RZA1_BCR_BASE + 0x0c)
+#define CS2WCR (RZA1_BCR_BASE + 0x30)
+#define CS3BCR (RZA1_BCR_BASE + 0x10)
+#define CS3WCR (RZA1_BCR_BASE + 0x34)
+#define SDCR (RZA1_BCR_BASE + 0x4c)
+#define RTCOR (RZA1_BCR_BASE + 0x58)
+#define RTCSR (RZA1_BCR_BASE + 0x50)
+
+#define SDRAM_MODE_CS2 0x3FFFD040 /* CS2: CAS=2, burst write, 16bit bus */
+#define SDRAM_MODE_CS3 0x3FFFE040 /* CS3: CAS=2, burst write, 16bit bus */
DECLARE_GLOBAL_DATA_PTR;
@@ -27,23 +37,101 @@ int board_init(void)
return 0;
}
-/*
- * The Genmai DT will most likely contain memory nodes describing the external
- * SDRAM memory connected to CS2 and CS3, however we do not yet have any code
- * in U-Boot to setup the memory controller. For now ignore DT and make use of
- * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE.
- */
+// nicked from pinctrl-rza1.c
+#define PINCTRL_BASE 0xfcfe3000
+#define PFC(b) (PINCTRL_BASE + 0x0500 + (b) * 4)
+#define PFCE(b) (PINCTRL_BASE + 0x0600 + (b) * 4)
+#define PMCSR(b) (PINCTRL_BASE + 0x0900 + (b) * 4)
+#define PFCAE(b) (PINCTRL_BASE + 0x0A00 + (b) * 4)
+#define PIBC(b) (PINCTRL_BASE + 0x4000 + (b) * 4)
+#define PBDC(b) (PINCTRL_BASE + 0x4100 + (b) * 4)
+#define PIPC(b) (PINCTRL_BASE + 0x4200 + (b) * 4)
+
+static void pinctrl(u16 ba, u16 li, u16 fu, u16 in, u16 bi)
+{
+ clrsetbits_le16(PFCAE(ba), BIT(li), (fu & BIT(2)) ? BIT(li) : 0);
+ clrsetbits_le16(PFCE(ba), BIT(li), (fu & BIT(1)) ? BIT(li) : 0);
+ clrsetbits_le16(PFC(ba), BIT(li), (fu & BIT(0)) ? BIT(li) : 0);
+ clrsetbits_le16(PIBC(ba), BIT(li), in ? BIT(li) : 0);
+ clrsetbits_le16(PBDC(ba), BIT(li), bi ? BIT(li) : 0);
+ setbits_le32(PMCSR(ba), BIT(li + 16) | BIT(li));
+ setbits_le16(PIPC(ba), BIT(li));
+}
+
+#define RZA1_PINMUX(bank, line, func) pinctrl(bank, line, (func) - 1, 0, 0)
+#define RZA1_PINMUX_BI(bank, line, func) pinctrl(bank, line, (func) - 1, 0, 1)
+
+void setup_external_memory(void)
+{
+ /* Dual 16-bit SDRAM 'IS42S16320B-75' on CS2 and CS3 */
+ RZA1_PINMUX_BI(6, 0, 1); /* P6_0 = D0 */
+ RZA1_PINMUX_BI(6, 1, 1); /* P6_1 = D1 */
+ RZA1_PINMUX_BI(6, 2, 1); /* P6_2 = D2 */
+ RZA1_PINMUX_BI(6, 3, 1); /* P6_3 = D3 */
+ RZA1_PINMUX_BI(6, 4, 1); /* P6_4 = D4 */
+ RZA1_PINMUX_BI(6, 5, 1); /* P6_5 = D5 */
+ RZA1_PINMUX_BI(6, 6, 1); /* P6_6 = D6 */
+ RZA1_PINMUX_BI(6, 7, 1); /* P6_7 = D7 */
+ RZA1_PINMUX_BI(6, 8, 1); /* P6_8 = D8 */
+ RZA1_PINMUX_BI(6, 9, 1); /* P6_9 = D9 */
+ RZA1_PINMUX_BI(6, 10, 1); /* P6_10 = D10 */
+ RZA1_PINMUX_BI(6, 11, 1); /* P6_11 = D11 */
+ RZA1_PINMUX_BI(6, 12, 1); /* P6_12 = D12 */
+ RZA1_PINMUX_BI(6, 13, 1); /* P6_13 = D13 */
+ RZA1_PINMUX_BI(6, 14, 1); /* P6_14 = D14 */
+ RZA1_PINMUX_BI(6, 15, 1); /* P6_15 = D15 */
+ RZA1_PINMUX(7, 9, 1); /* P7_9 = A1 */
+ RZA1_PINMUX(7, 10, 1); /* P7_10 = A2 */
+ RZA1_PINMUX(7, 11, 1); /* P7_11 = A3 */
+ RZA1_PINMUX(7, 12, 1); /* P7_12 = A4 */
+ RZA1_PINMUX(7, 13, 1); /* P7_13 = A5 */
+ RZA1_PINMUX(7, 14, 1); /* P7_14 = A6 */
+ RZA1_PINMUX(7, 15, 1); /* P7_15 = A7 */
+ RZA1_PINMUX(8, 0, 1); /* P8_0 = A8 */
+ RZA1_PINMUX(8, 1, 1); /* P8_1 = A9 */
+ RZA1_PINMUX(8, 2, 1); /* P8_2 = A10 */
+ RZA1_PINMUX(8, 3, 1); /* P8_3 = A11 */
+ RZA1_PINMUX(8, 4, 1); /* P8_4 = A12 */
+ RZA1_PINMUX(8, 5, 1); /* P8_5 = A13 */
+ RZA1_PINMUX(8, 6, 1); /* P8_6 = A14 */
+ RZA1_PINMUX(8, 7, 1); /* P8_7 = A15 */
+ RZA1_PINMUX(7, 2, 1); /* P7_2 = RAS */
+ RZA1_PINMUX(7, 3, 1); /* P7_3 = CAS */
+ RZA1_PINMUX(7, 4, 1); /* P7_4 = CKE */
+ RZA1_PINMUX(7, 5, 1); /* P7_5 = RDWR */
+ RZA1_PINMUX(7, 6, 1); /* P7_6 = WE0/DQMLL */
+ RZA1_PINMUX(7, 7, 1); /* P7_7 = DQMLU */
+ RZA1_PINMUX(5, 8, 6); /* P5_8 = CS2 */
+ RZA1_PINMUX(7, 1, 1); /* P7_1 = CS3 */
+
+ /**********************************************/
+ /* Configure SDRAM (CS2, CS3) */
+ /**********************************************/
+
+ writel(0x00004c00, CS2BCR);
+ writel(0x00000080, CS2WCR);
+ writel(0x00004c00, CS3BCR);
+ writel(0x00002492, CS3WCR);
+ writel(0x00120812, SDCR);
+ writel(0xa55a0020, RTCOR);
+ writel(0xa55a0010, RTCSR);
+
+ for (int i = 0; i < 0x33f1; i++)
+ asm("nop");
+
+ writew(0, SDRAM_MODE_CS2);
+ writew(0, SDRAM_MODE_CS3);
+}
int dram_init(void)
{
- gd->ram_base = CFG_SYS_SDRAM_BASE;
- gd->ram_size = 10 << 20;
- return 0;
+ /* 64 MiB SDRAM at 0x08000000 + 64 MiB SDRAM at 0x0c000000 */
+ setup_external_memory();
+
+ return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = gd->ram_size;
- return 0;
+ return fdtdec_setup_memory_banksize();
}
--- 0001/configs/genmai_defconfig
+++ work/configs/genmai_defconfig 2025-07-11 16:03:57.655983739 +0900
@@ -7,6 +7,11 @@ CONFIG_POSITION_INDEPENDENT=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-genmai"
CONFIG_TARGET_GENMAI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x08000000
+CONFIG_SYS_MEMTEST_END=0x10000000
+CONFIG_CMD_MEMTEST=y
+
CONFIG_ENV_IS_IN_MTD=y
CONFIG_ENV_MTD_DEV="nor0"
CONFIG_ENV_OFFSET=0x80000
--- 0001/configs/grpeach_defconfig
+++ work/configs/grpeach_defconfig 2025-07-11 16:04:10.694062244 +0900
@@ -6,6 +6,8 @@ CONFIG_TEXT_BASE=0x18000000
CONFIG_DEFAULT_DEVICE_TREE="renesas/r7s72100-gr-peach"
CONFIG_TARGET_GRPEACH=y
+CONFIG_NR_DRAM_BANKS=1
+
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
--- 0001/configs/renesas_rza1.config
+++ work/configs/renesas_rza1.config 2025-07-11 16:02:42.505531236 +0900
@@ -31,7 +31,6 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MAC_PARTITION=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_CONTROL=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PHY_SMSC=y
--- 0001/dts/upstream/src/arm/renesas/r7s72100-genmai.dts
+++ work/dts/upstream/src/arm/renesas/r7s72100-genmai.dts 2025-07-11
16:02:42.506531242 +0900
@@ -54,6 +54,11 @@
};
};
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x00a00000>;
+ };
+
keyboard {
compatible = "gpio-keys";
@@ -83,11 +88,6 @@
};
};
- memory@8000000 {
- device_type = "memory";
- reg = <0x08000000 0x08000000>;
- };
-
cvcc2: regulator-mmc {
compatible = "regulator-fixed";
regulator-name = "Cvcc2";
@@ -152,6 +152,18 @@
};
};
};
+
+ /* 64 MiB SDRAM connected to CS2 */
+ memory@8000000 {
+ device_type = "memory";
+ reg = <0x08000000 0x04000000>;
+ };
+
+ /* 64 MiB SDRAM connected to CS3 */
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x04000000>;
+ };
};
ðer {
