any feedback for this patch? Thanks. Roy > -----Original Message----- > From: Zang Roy-R61911 > Sent: Thursday, June 09, 2011 11:31 AM > To: [email protected] > Cc: Zang Roy-R61911; Wang Haiying-R54964; Lan Chunhe-B25806; Xu Lei-B33228; > sun york-R58495; Kumar Gala > Subject: [PATCH v2] powerpc/85xx: Add basic support for P1023RDS board > > The P1023RDS board is the reference board for the P1023 SoC. > > Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, > UART, I2C, etc. > > Signed-off-by: Roy Zang <[email protected]> > Signed-off-by: Haiying Wang <[email protected]> > Signed-off-by: Chunhe Lan <[email protected]> > Signed-off-by: Lei Xu <[email protected]> > Signed-off-by: York Sun <[email protected]> > Signed-off-by: Kumar Gala <[email protected]> > --- > based on "Prepare v2011.06-rc2" > v2 vs. v1: some code style clean up > > MAINTAINERS | 1 + > board/freescale/p1023rds/Makefile | 38 ++ > board/freescale/p1023rds/bcsr.h | 53 +++ > board/freescale/p1023rds/law.c | 35 ++ > board/freescale/p1023rds/p1023rds.c | 162 +++++++ > board/freescale/p1023rds/tlb.c | 118 ++++++ > boards.cfg | 2 + > doc/README.p1023rds | 102 +++++ > include/configs/P1023RDS.h | 562 > +++++++++++++++++++++++++ > nand_spl/board/freescale/p1023rds/Makefile | 133 ++++++ > nand_spl/board/freescale/p1023rds/nand_boot.c | 99 +++++ > 11 files changed, 1305 insertions(+), 0 deletions(-) > create mode 100644 board/freescale/p1023rds/Makefile > create mode 100644 board/freescale/p1023rds/bcsr.h > create mode 100644 board/freescale/p1023rds/law.c > create mode 100644 board/freescale/p1023rds/p1023rds.c > create mode 100644 board/freescale/p1023rds/tlb.c > create mode 100644 doc/README.p1023rds > create mode 100644 include/configs/P1023RDS.h > create mode 100644 nand_spl/board/freescale/p1023rds/Makefile > create mode 100644 nand_spl/board/freescale/p1023rds/nand_boot.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index c462ae2..af31552 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -511,6 +511,7 @@ Ilya Yanok <[email protected]> > Roy Zang <[email protected]> > > mpc7448hpc2 MPC7448 > + P1023RDS P1023 > > John Zhan <[email protected]> > > diff --git a/board/freescale/p1023rds/Makefile > b/board/freescale/p1023rds/Makefile > new file mode 100644 > index 0000000..bf87580 > --- /dev/null > +++ b/board/freescale/p1023rds/Makefile > @@ -0,0 +1,38 @@ > +# > +# Copyright 2010-2011 Freescale Semiconductor, Inc. > +# > +# This program is free software; you can redistribute it and/or modify it > +# under the terms of the GNU General Public License as published by the Free > +# Software Foundation; either version 2 of the License, or (at your option) > +# any later version. > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS-y += $(BOARD).o > +COBJS-y += law.o > +COBJS-y += tlb.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS-y)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(AR) $(ARFLAGS) $@ $(OBJS) > + > +clean: > + rm -f $(OBJS) $(SOBJS) > + > +distclean: clean > + rm -f $(LIB) core *.bak .depend > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/freescale/p1023rds/bcsr.h b/board/freescale/p1023rds/bcsr.h > new file mode 100644 > index 0000000..0995aa4 > --- /dev/null > +++ b/board/freescale/p1023rds/bcsr.h > @@ -0,0 +1,53 @@ > +/* > + * Copyright (C) 2011 Freescale Semiconductor, Inc. > + * > + * Authors: Chunhe Lan <[email protected]> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the Free > + * Software Foundation; either version 2 of the License, or (at your option) > + * any later version. > + * > + */ > + > +#ifndef __BCSR_H_ > +#define __BCSR_H_ > + > +#include <common.h> > + > +/* > + * BCSR Bit definitions > + * BCSR 15 * > + 0 device insertion oriention > + 1 stack processor present > + 2 power supply shut down/normal operation > + 3 I2C bus0 drive enable > + 4 reserved > + 5:7 I2C bus0 select > + 5 - I2C_BUS_0_SS0 > + 6 - I2C_BUS_0_SS1 > + 7 - I2C_BUS_0_SS2 > +*/ > + > +/* BCSR register base address is 0xFX000020 */ > +#define BCSR_BASE_REG_OFFSET 0x20 > +#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) > + > +#define BCSR15_DEV_INS_ORI 0x80 > +#define BCSR15_STACK_PRO_PRE 0x40 > +#define BCSR15_POWER_SUPPLY 0x20 > +#define BCSR15_I2C_BUS0_EN 0x10 > +#define BCSR15_I2C_BUS0_SEG0 0x00 > +#define BCSR15_I2C_BUS0_SEG1 0x04 > +#define BCSR15_I2C_BUS0_SEG2 0x02 > +#define BCSR15_I2C_BUS0_SEG3 0x06 > +#define BCSR15_I2C_BUS0_SEG4 0x01 > +#define BCSR15_I2C_BUS0_SEG5 0x05 > +#define BCSR15_I2C_BUS0_SEG6 0x03 > +#define BCSR15_I2C_BUS0_SEG7 0x07 > +#define BCSR15_I2C_BUS0_SEG_CLR 0x07 > +#define BCSR19_SGMII_SEL_L 0x01 > + > +/*BCSR Utils functions*/ > +void fixup_i2c_bus0_sel_seg0(void); > +#endif /* __BCSR_H_ */ > diff --git a/board/freescale/p1023rds/law.c b/board/freescale/p1023rds/law.c > new file mode 100644 > index 0000000..f140f64 > --- /dev/null > +++ b/board/freescale/p1023rds/law.c > @@ -0,0 +1,35 @@ > +/* > + * Copyright 2010-2011 Freescale Semiconductor, Inc. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/fsl_law.h> > +#include <asm/mmu.h> > + > +struct law_entry law_table[] = { > + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), > + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, > + LAW_TRGT_IF_DPAA_SWP_SRAM), > + /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */ > + SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), > +}; > + > +int num_law_entries = ARRAY_SIZE(law_table); > diff --git a/board/freescale/p1023rds/p1023rds.c > b/board/freescale/p1023rds/p1023rds.c > new file mode 100644 > index 0000000..8cfd199 > --- /dev/null > +++ b/board/freescale/p1023rds/p1023rds.c > @@ -0,0 +1,162 @@ > +/* > + * Copyright 2010-2011 Freescale Semiconductor, Inc. > + * > + * Authors: Roy Zang <[email protected]> > + * Chunhe Lan <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <command.h> > +#include <pci.h> > +#include <asm/io.h> > +#include <asm/cache.h> > +#include <asm/processor.h> > +#include <asm/mmu.h> > +#include <asm/immap_85xx.h> > +#include <asm/fsl_pci.h> > +#include <asm/fsl_ddr_sdram.h> > +#include <asm/fsl_portals.h> > +#include <libfdt.h> > +#include <fdt_support.h> > +#include <netdev.h> > +#include <malloc.h> > + > +#include "bcsr.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_early_init_f(void) > +{ > + fsl_lbc_t *lbc = LBC_BASE_ADDR; > + > + /* Set ABSWP to implement conversion of addresses in the LBC */ > + setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); > + > + return 0; > +} > + > +int checkboard(void) > +{ > + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; > + > + printf("Board: P1023 RDS\n"); > + > + clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR); > + setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0); > + > + return 0; > +} > + > +/* Fixed sdram init -- doesn't use serial presence detect. */ > +phys_size_t fixed_sdram(void) > +{ > +#ifndef CONFIG_SYS_RAMBOOT > + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; > + > + set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); > + > + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); > + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); > + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); > + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); > + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); > + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); > + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); > + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); > + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); > + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); > + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); > + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); > + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); > + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); > + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); > + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); > + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); > + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); > + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); > + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); > + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); > +#endif > + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; > +} > + > +#ifdef CONFIG_PCI > +void pci_init_board(void) > +{ > + fsl_pcie_init_board(0); > +} > +#endif > + > +int board_early_init_r(void) > +{ > + const unsigned int flashbase = CONFIG_SYS_BCSR_BASE; > + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); > + > + /* > + * Remap Boot flash + BCSR region to caching-inhibited > + * so that flash can be erased properly. > + */ > + > + /* Flush d-cache and invalidate i-cache of any FLASH data */ > + flush_dcache(); > + invalidate_icache(); > + > + /* invalidate existing TLB entry for flash + bcsr */ > + disable_tlb(flash_esel); > + > + set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, flash_esel, BOOKE_PAGESZ_256M, 1); > + > + setup_portals(); > + > + return 0; > +} > + > +unsigned long get_board_sys_clk(ulong dummy) > +{ > + return gd->bus_clk; > +} > + > +unsigned long get_board_ddr_clk(ulong dummy) > +{ > + return gd->mem_clk; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + return pci_eth_init(bis); > +} > + > +#if defined(CONFIG_OF_BOARD_SETUP) > +void ft_board_setup(void *blob, bd_t *bd) > +{ > + phys_addr_t base; > + phys_size_t size; > + > + ft_cpu_setup(blob, bd); > + > + base = getenv_bootm_low(); > + size = getenv_bootm_size(); > + > + fdt_fixup_memory(blob, (u64)base, (u64)size); > +} > +#endif > diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c > new file mode 100644 > index 0000000..2b3b679 > --- /dev/null > +++ b/board/freescale/p1023rds/tlb.c > @@ -0,0 +1,118 @@ > +/* > + * Copyright 2010-2011 Freescale Semiconductor, Inc. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/mmu.h> > + > +struct fsl_e_tlb_entry tlb_table[] = { > + /* TLB 0 - for temp stack in cache */ > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + /* TLB 1 */ > + /* *I*** - Covers boot page */ > + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, > + 0, 0, BOOKE_PAGESZ_4K, 1), > + > + /* *I*G* - CCSRBAR */ > + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 1, BOOKE_PAGESZ_4M, 1), > + > +#ifndef CONFIG_NAND_SPL > + /* *W*G* - BCSR and NOR flash on local bus*/ > + /* This will be changed to *I*G* after relocation to RAM. */ > + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, > + 0, 2, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 3, BOOKE_PAGESZ_1G, 1), > + > + /* *I*G* - PCI */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 4, BOOKE_PAGESZ_256M, 1), > + > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 5, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI I/O */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 6, BOOKE_PAGESZ_256K, 1), > + > + /* Bman/Qman */ > + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 7, BOOKE_PAGESZ_1M, 1), > + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, > + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 8, BOOKE_PAGESZ_1M, 1), > + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, > + 0, 9, BOOKE_PAGESZ_1M, 1), > + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, > + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 10, BOOKE_PAGESZ_1M, 1), > +#endif > + > + /* *I*G - NAND */ > + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 11, BOOKE_PAGESZ_1M, 1), > + > +#ifdef CONFIG_SYS_RAMBOOT > + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, > + CONFIG_SYS_DDR_SDRAM_BASE, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 12, BOOKE_PAGESZ_1G, 1), > + > + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, > + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 13, BOOKE_PAGESZ_1G, 1), > +#endif > +}; > + > +int num_tlb_entries = ARRAY_SIZE(tlb_table); > diff --git a/boards.cfg b/boards.cfg > index d2cacc8..ee775bd 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -556,6 +556,8 @@ P1020RDB_SDCARD powerpc mpc85xx > p1_p2_rdb freesca > P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb > freescale - P1_P2_RDB:P1020RDB,SPIFLASH > P1022DS powerpc mpc85xx p1022ds > freescale > P1022DS_36BIT powerpc mpc85xx p1022ds > freescale - P1022DS:36BIT > +P1023RDS powerpc mpc85xx p1023rds > freescale - P1023RDS > +P1023RDS_NAND powerpc mpc85xx p1023rds > freescale - P1023RDS:NAND > P2010RDB powerpc mpc85xx p1_p2_rdb > freescale - P1_P2_RDB:P2010RDB > P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb > freescale - P1_P2_RDB:P2010RDB,36BIT > P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb > freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD > diff --git a/doc/README.p1023rds b/doc/README.p1023rds > new file mode 100644 > index 0000000..657bd67 > --- /dev/null > +++ b/doc/README.p1023rds > @@ -0,0 +1,102 @@ > +Overview > +-------- > +The P1023 process includes a performance optimized implementation of the > +QorIQ data Path Acceleration Architecture (DPAA). This architecture > +provides the infrastructure to support simplified sharing of networking > +interfaces and accelerators by multiple CPU cores. P1023 is an e500 based > +dual core SOC. > + > +P1023RDS board is a Low End Dual core platform supporting the P1023 > +processor of QorIQ series. > + > +Building U-boot > +--------------- > +To build the u-boot for P1023RDS: > +Configure to NOR boot: > + make P1023RDS_config > +Configure to NAND boot: > + make P1023RDS_NAND_config > +Build: > + make > + > +Board Switches > +-------------- > +Most switches on the board should not be changed. The most frequent > +user-settable switches on the board are used to configure > +the flash banks. > + > +J4: all open > + > +Default NOR flash boot switch setting: > + Sw3[1:8]: off on on off on on off off > + Sw4[1:8]: off off off on off off off off > + Sw6[1:8]: off on off on off on on off > + Sw7[1:8]: off on off off on off off off > + Sw8[1:8]: on off off off off off off off > + > +For NAND flash boot,set > +Sw4[1:4]: off on on on > + > +The default native ethernet setting is for RGMII mode. > +To use SGMII mode, set > +SW8[1:2]: OFF OFF > +SW7[6:7]: ON ON > + > +Memory Map > +---------- > +0x0000_0000 0x7fff_ffff DDR 2G Cacheable > +0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable > +0xc000_0000 0xdfff_ffff PCI 512M non-cacheable > +0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable > + > +0xe000_0000 0xe003_ffff BCSR 256K BCSR > +0xee00_0000 0xefff_ffff NOR flash 32M NOR flash > +0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M > +0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable > +0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable > +0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 > + > +Flashing u-boot Images > +--------------- > +To program the image in the boot flash bank: > +NOR flash boot: > + => tftp 1000000 u-boot.bin > + => protect off all > + => erase eff80000 efffffff > + => cp.b 1000000 eff80000 80000 > + > +NAND flash boot: > + => tftp 1000000 u-boot-nand.bin > + => nand erase 0 80000 > + => nand write 1000000 0 80000 > + > +Firmware ucode location > +--------------------------------- > +Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. > +u-boot loads ucode FLASH. The location for ucode: > +NOR Flash: 0xfe000000 > +NAND Flash: 0x1f00000 > + > +Using the Device Tree Source File > +--------------------------------- > +To create the DTB (Device Tree Binary) image file, > +use a command similar to this: > + > + dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb > + > +Likely, that .dts file will come from here; > + > + linux-2.6/arch/powerpc/boot/dts/p1023rds.dts > +or > + make p1023rds.dtb ARCH=powerpc > +in linux-2.6 directory. > + > +Booting Linux > +------------- > +Place a linux uImage in the TFTP disk area. > + > + tftp 1000000 uImage > + tftp 2000000 rootfs.ext2.gz.uboot > + tftp c00000 p1023rds.dtb > + bootm 1000000 2000000 c00000 > + > diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h > new file mode 100644 > index 0000000..4f14a02 > --- /dev/null > +++ b/include/configs/P1023RDS.h > @@ -0,0 +1,562 @@ > +/* > + * Copyright 2010-2011 Freescale Semiconductor, Inc. > + * > + * Authors: Roy Zang <[email protected]> > + * Chunhe Lan <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * p1023rds board configuration file > + * > + */ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#ifdef CONFIG_NAND > +#define CONFIG_NAND_U_BOOT > +#define CONFIG_RAMBOOT_NAND > +#endif > + > +#ifdef CONFIG_NAND_U_BOOT > +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 > +#define CONFIG_SYS_TEXT_BASE 0x11001000 > + > +#ifdef CONFIG_NAND_SPL > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of > monitor > */ > +#else > +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of > monitor > */ > +#endif /* CONFIG_NAND_SPL */ > +#endif > + > +#ifndef CONFIG_SYS_TEXT_BASE > +#define CONFIG_SYS_TEXT_BASE 0xeff80000 > +#endif > + > +#ifndef CONFIG_SYS_MONITOR_BASE > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of > monitor > */ > +#endif > + > +#ifndef CONFIG_RESET_VECTOR_ADDRESS > +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc > +#endif > + > +/* High Level Configuration Options */ > +#define CONFIG_BOOKE /* BOOKE */ > +#define CONFIG_E500 /* BOOKE e500 family */ > +#define CONFIG_MPC85xx > +#define CONFIG_P1023 > +#define CONFIG_P1023RDS > +#define CONFIG_MP /* support multiple processors */ > + > +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ > +#define CONFIG_PCI /* Enable PCI/PCIE */ > +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ > +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ > +#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ > +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > +#define CONFIG_FSL_LAW /* Use common FSL init code */ > + > +#ifndef __ASSEMBLY__ > +extern unsigned long get_clock_freq(void); > +#endif > + > +#define CONFIG_SYS_CLK_FREQ 66666666 > +#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ > + > +/* > + * These can be toggled for performance analysis, otherwise use default. > + */ > +#define CONFIG_L2_CACHE /* toggle L2 cache */ > +#define CONFIG_BTB /* toggle branch predition */ > +#define CONFIG_HWCONFIG > + > +#define CONFIG_ENABLE_36BIT_PHYS > + > +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ > +#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only > 1G */ > +#define CONFIG_PANIC_HANG /* do not reset board on panic */ > + > +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of > + addresses in the LBC */ > +/* > + * Base addresses -- Note these are effective addresses where the > + * actual resources get mapped (not physical addresses) > + */ > +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */ > +#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */ > +/* physical addr of CCSRBAR */ > +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR > +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses > CONFIG_SYS_IMMR */ > + > +/* DDR Setup */ > +#define CONFIG_VERY_BIG_RAM > + > +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER > +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef > + > +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 > +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE > + > +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 > +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 > + > +/* These are used when DDR doesn't use SPD. */ > +#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */ > + > +/* Default settings for "stable" mode */ > +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F > +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F > +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 > +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 > +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 > +#define CONFIG_SYS_DDR_TIMING_0 0x40110104 > +#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544 > +#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA > +#define CONFIG_SYS_DDR_MODE_1 0x00441210 > +#define CONFIG_SYS_DDR_MODE_2 0x00000000 > +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 > +#define CONFIG_SYS_DDR_INTERVAL 0x0A280100 > +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef > +#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000 > +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 > +#define CONFIG_SYS_DDR_TIMING_5 0x01401400 > +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 > +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605 > +#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No > Interleaving */ > +#define CONFIG_SYS_DDR_CONTROL2 0x24401010 > +#define CONFIG_SYS_DDR_CDR1 0x00000000 > +#define CONFIG_SYS_DDR_CDR2 0x00000000 > + > +#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 > +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 > +#define CONFIG_SYS_DDR_SBE 0x00000000 > + > +/* Settings that differ for "performance" mode */ > +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ > +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ > +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302 > +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544 > +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA > +/* Type = DDR3: cs0-cs1 interleaving */ > +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008 > +#define CONFIG_SYS_DDR_CDR_1 0x00000000 > +#define CONFIG_SYS_DDR_CDR_2 0x00000000 > + > + > +/* > + * Memory map > + * > + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable > + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable > + * 0xc000_0000 0xdfff_ffff PCI 512M > non-cacheable > + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable > + * > + * Localbus non-cacheable > + * 0xe000_0000 0xe003_ffff BCSR 256K BCSR > + * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash > + * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M > + * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable > + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable > + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable > TLB0 > + */ > + > +/* > + * Local Bus Definitions > + */ > +#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */ > +#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE > + > +#ifndef CONFIG_NAND > +#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH > 32M */ > + > +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE > + > +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ > + | BR_PS_16 | BR_V) > +#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 > + > +#define CONFIG_FLASH_CFI_DRIVER > +#define CONFIG_SYS_FLASH_CFI > +#define CONFIG_SYS_FLASH_EMPTY_INFO > + > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ > +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ > +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ > +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ > +#else > +#define CONFIG_SYS_NO_FLASH > +#endif > + > +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) > +#define CONFIG_SYS_RAMBOOT > +#endif > + > +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ > +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ > + > +#define CONFIG_SYS_INIT_RAM_LOCK > +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ > +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in > RAM */ > + > +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ > +#define CONFIG_SYS_GBL_DATA_OFFSET \ > + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > + > +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon > */ > +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for > malloc */ > + > +#ifndef CONFIG_NAND_SPL > +#define CONFIG_SYS_NAND_BASE 0xffa00000 > +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE > +#else > +#define CONFIG_SYS_NAND_BASE 0xfff00000 > +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE > +#endif > + > +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define CONFIG_MTD_NAND_VERIFY_WRITE > +#define CONFIG_CMD_NAND > +#define CONFIG_NAND_FSL_ELBC > +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) > + > +/* NAND boot: 4K NAND loader config */ > +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 > +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) > +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) > +#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 > +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) > +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 > +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + > 0x10000) > + > +/* NAND flash config */ > +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ > + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ > + | BR_PS_8 /* Port Size = 8bit */ \ > + | BR_MS_FCM /* MSEL = FCM */ \ > + | BR_V) /* valid */ > +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K > */ \ > + | OR_FCM_CSCT \ > + | OR_FCM_CST \ > + | OR_FCM_CHT \ > + | OR_FCM_SCY_1 \ > + | OR_FCM_TRLX \ > + | OR_FCM_EHTR) > + > +#ifdef CONFIG_RAMBOOT_NAND > +/* NAND Base Address */ > +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM > +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND > Options */ > +/* chip select 1 - BCSR */ > +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ > + | BR_MS_GPCM | BR_PS_8 | BR_V) > +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ > + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ > + | OR_GPCM_EAD) > +#else > +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base > Address > */ > +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options > */ > +/* chip select 1 - BCSR */ > +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ > + | BR_MS_GPCM | BR_PS_8 | BR_V) > +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ > + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ > + | OR_GPCM_EAD) > +#endif > + > +/* Serial Port > + * open - index 2 > + * shorted - index 1 > + */ > +#define CONFIG_CONS_INDEX 1 > +#undef CONFIG_SERIAL_SOFTWARE_FIFO > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE 1 > +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) > +#ifdef CONFIG_NAND_SPL > +#define CONFIG_NS16550_MIN_FUNCTIONS > +#endif > + > +#define CONFIG_SYS_BAUDRATE_TABLE \ > + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} > + > +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) > +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) > + > +/* Use the HUSH parser */ > +#define CONFIG_SYS_HUSH_PARSER > +#ifdef CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#endif > + > +/* > + * Pass open firmware flat tree > + */ > +#define CONFIG_OF_LIBFDT > +#define CONFIG_OF_BOARD_SETUP > +#define CONFIG_OF_STDOUT_VIA_ALIAS > + > +#define CONFIG_SYS_64BIT_VSPRINTF > +#define CONFIG_SYS_64BIT_STRTOUL > + > +/* new uImage format support */ > +#define CONFIG_FIT > +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ > + > +/* I2C */ > +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ > +#define CONFIG_HARD_I2C /* I2C with hardware support */ > +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ > +#define CONFIG_I2C_MULTI_BUS > +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 > +#define CONFIG_SYS_I2C_SLAVE 0x7F > +#define CONFIG_SYS_I2C_OFFSET 0x3000 > +#define CONFIG_SYS_I2C2_OFFSET 0x3100 > + > +/* > + * I2C2 EEPROM > + */ > +#define CONFIG_ID_EEPROM > +#ifdef CONFIG_ID_EEPROM > +#define CONFIG_SYS_I2C_EEPROM_NXID > +#endif > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 > +#define CONFIG_SYS_EEPROM_BUS_NUM 0 > + > +#define CONFIG_CMD_I2C > + > +/* > + * eSPI - Enhanced SPI > + */ > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_ATMEL > + > +#define CONFIG_HARD_SPI > +#define CONFIG_FSL_ESPI > + > +#define CONFIG_CMD_SF > +#define CONFIG_SF_DEFAULT_SPEED 10000000 > +#define CONFIG_SF_DEFAULT_MODE 0 > + > +/* > + * General PCI > + * Memory space is mapped 1-1, but I/O space must start from 0. > + */ > + > +/* controller 3, Slot 1, tgtid 3, Base address b000 */ > +#define CONFIG_SYS_PCIE3_NAME "Slot 3" > +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 > +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 > +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 > +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 > +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ > + > +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ > +#define CONFIG_SYS_PCIE2_NAME "Slot 2" > +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 > +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 > +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > + > +/* controller 1, Slot 2, tgtid 1, Base address a000 */ > +#define CONFIG_SYS_PCIE1_NAME "Slot 1" > +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 > +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 > +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > + > +#if defined(CONFIG_PCI) > +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ > +#define CONFIG_NET_MULTI > +#define CONFIG_PCI_PNP /* do pci plug-and-play */ > +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ > +#endif /* CONFIG_PCI */ > + > +#ifndef CONFIG_NET_MULTI > +#define CONFIG_NET_MULTI > +#endif > + > +/* > + * Environment > + */ > +#define CONFIG_ENV_OVERWRITE > + > +#if defined(CONFIG_SYS_RAMBOOT) > +#if defined(CONFIG_RAMBOOT_NAND) > +#define CONFIG_ENV_IS_IN_NAND > +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE > +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) > +#else > +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ > +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000) > +#define CONFIG_ENV_SIZE 0x2000 > +#endif > +#else > +#define CONFIG_ENV_IS_IN_FLASH > +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 > +#define CONFIG_ENV_ADDR 0xfff80000 > +#else > +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - > CONFIG_ENV_SECT_SIZE) > +#endif > +#define CONFIG_ENV_SIZE 0x2000 > +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ > +#endif > + > +#define CONFIG_LOADS_ECHO /* echo on for serial download */ > +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ > + > +/* > + * Command line configuration. > + */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_IRQ > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_ELF > +#define CONFIG_CMD_SETEXPR > +#define CONFIG_CMD_REGINFO > + > +#if defined(CONFIG_PCI) > +#define CONFIG_CMD_PCI > +#define CONFIG_CMD_NET > +#endif > + > +/* > + * USB > + */ > +#define CONFIG_USB_EHCI > + > +#ifdef CONFIG_USB_EHCI > +#define CONFIG_CMD_USB > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET > +#define CONFIG_USB_EHCI_FSL > +#define CONFIG_USB_STORAGE > +#define CONFIG_CMD_FAT > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > +#endif > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ > +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ > +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ > +#if defined(CONFIG_CMD_KGDB) > +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ > +#else > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +#endif > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > +/* Boot Argument Buffer Size */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks > */ > + > +/* > + * For booting Linux, the board info and command line data > + * have to be in the first 16 MB of memory, since this is > + * the maximum mapped by the Linux kernel during initialization. > + */ > +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ > +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ > + > +#if defined(CONFIG_CMD_KGDB) > +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ > +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ > +#endif > + > +/* > + * Environment Configuration > + */ > +#define CONFIG_BOOTFILE uImage > +#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ > + > +/* default location for tftp and bootm */ > +#define CONFIG_LOADADDR 1000000 > + > +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ > + > +#define CONFIG_BAUDRATE 115200 > + > +/* Qman/Bman */ > +#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ > +#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 > +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE > +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 > +#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 > +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE > +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 > + > +/* For FM */ > +#define CONFIG_SYS_DPAA_FMAN > +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ > + > +#ifdef CONFIG_SYS_DPAA_FMAN > +#define CONFIG_FMAN_ENET > +#endif > + > +#ifndef CONFIG_NAND > +/* Default address of microcode for the Linux Fman driver */ > +/* QE microcode/firmware address */ > +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 > +#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR > +#else > +#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 > +#define CONFIG_SYS_FMAN_FW_ADDR 0x10000000 > +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 > +#endif > + > +#ifdef CONFIG_FMAN_ENET > +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 > +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7 > + > +#define CONFIG_SYS_TBIPA_VALUE 8 > +#define CONFIG_MII /* MII PHY management */ > +#define CONFIG_ETHPRIME "FM1@DTSEC1" > +#endif > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" > + > +#endif /* __CONFIG_H */ > diff --git a/nand_spl/board/freescale/p1023rds/Makefile > b/nand_spl/board/freescale/p1023rds/Makefile > new file mode 100644 > index 0000000..9e03830 > --- /dev/null > +++ b/nand_spl/board/freescale/p1023rds/Makefile > @@ -0,0 +1,133 @@ > +# > +# Copyright 2010-2011 Freescale Semiconductor, Inc. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > +NAND_SPL := y > +PAD_TO := 0xfff01000 > + > +include $(TOPDIR)/config.mk > + > +nandobj := $(OBJTREE)/nand_spl/ > + > +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds > +LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext > $(CONFIG_SYS_TEXT_BASE_SPL) > \ > + $(LDFLAGS) $(LDFLAGS_FINAL) > +AFLAGS += -DCONFIG_NAND_SPL > +CFLAGS += -DCONFIG_NAND_SPL > + > +SOBJS = start.o resetvec.o > +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ > + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o > + > +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) > +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) > +__OBJS := $(SOBJS) $(COBJS) > +LNDIR := $(nandobj)board/$(BOARDDIR) > + > +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl- > 16k.bin > + > +all: $(obj).depend $(ALL) > + > +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl > + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ > + > +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl > + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ > + > +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds > + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ > + -Map $(nandobj)u-boot-spl.map \ > + -o $(nandobj)u-boot-spl > + > +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) > + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ > + > +# create symbolic links for common files > + > +$(obj)cache.c: > + @rm -f $(obj)cache.c > + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c > + > +$(obj)cpu_init_early.c: > + @rm -f $(obj)cpu_init_early.c > + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c > + > +$(obj)cpu_init_nand.c: > + @rm -f $(obj)cpu_init_nand.c > + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c > + > +$(obj)fsl_law.c: > + @rm -f $(obj)fsl_law.c > + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c > + > +$(obj)law.c: > + @rm -f $(obj)law.c > + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c > + > +$(obj)nand_boot_fsl_elbc.c: > + @rm -f $(obj)nand_boot_fsl_elbc.c > + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ > + $(obj)nand_boot_fsl_elbc.c > + > +$(obj)ns16550.c: > + @rm -f $(obj)ns16550.c > + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c > + > +$(obj)resetvec.S: > + @rm -f $(obj)resetvec.S > + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S > + > +$(obj)fixed_ivor.S: > + @rm -f $(obj)fixed_ivor.S > + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S > + > +$(obj)start.S: $(obj)fixed_ivor.S > + @rm -f $(obj)start.S > + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S > + > +$(obj)tlb.c: > + @rm -f $(obj)tlb.c > + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c > + > +$(obj)tlb_table.c: > + @rm -f $(obj)tlb_table.c > + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c > + > +ifneq ($(OBJTREE), $(SRCTREE)) > +$(obj)nand_boot.c: > + @rm -f $(obj)nand_boot.c > + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c > $(obj)nand_boot.c > +endif > + > +######################################################################### > + > +$(obj)%.o: $(obj)%.S > + $(CC) $(AFLAGS) -c -o $@ $< > + > +$(obj)%.o: $(obj)%.c > + $(CC) $(CFLAGS) -c -o $@ $< > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > + > diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c > b/nand_spl/board/freescale/p1023rds/nand_boot.c > new file mode 100644 > index 0000000..0065c87 > --- /dev/null > +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c > @@ -0,0 +1,99 @@ > +/* > + * Copyright 2010-2011 Freescale Semiconductor, Inc. > + * Author: Roy Zang <[email protected]> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + * > + */ > + > +#include <common.h> > +#include <ns16550.h> > +#include <asm/io.h> > +#include <nand.h> > +#include <asm/fsl_law.h> > + > +/* Fixed sdram init -- doesn't use serial presence detect. */ > +void sdram_init(void) > +{ > + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; > + > + set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); > + > + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); > + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); > + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); > + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); > + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); > + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); > + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); > + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); > + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); > + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); > + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); > + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); > + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); > + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); > + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); > + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); > + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); > + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); > + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); > + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); > + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); > +} > + > +void board_init_f(ulong bootflag) > +{ > + u32 plat_ratio, bus_clk; > + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; > + > + /* initialize selected port with appropriate baud rate */ > + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; > + plat_ratio >>= 1; > + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; > + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, > + bus_clk / 16 / CONFIG_BAUDRATE); > + > + puts("\nNAND boot... "); > + /* Initialize the DDR3 */ > + sdram_init(); > + /* copy code to RAM and jump to it - this should not return */ > + /* NOTE - code has to be copied out of NAND buffer before > + * other blocks can be read. > + */ > + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, > + CONFIG_SYS_NAND_U_BOOT_RELOC); > +} > + > +void board_init_r(gd_t *gd, ulong dest_addr) > +{ > + nand_boot(); > +} > + > +void putc(char c) > +{ > + if (c == '\n') > + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); > + > + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); > +} > + > +void puts(const char *str) > +{ > + while (*str) > + putc(*str++); > +} > -- > 1.6.0.6
_______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
