From: Dinesh Maniyam <dinesh.mani...@intel.com> With Inline ECC enabled, the bottom 1/8 of DDR is reserved for ECC parity bits and must not be used for general data address allocation. Previously, the SPL bss and malloc addresses were allocated inside this ECC parity region if the DDR size is 1GB.
This caused ECC hardware to detect stale or invalid parity bits, leading to data correction attempts and DMA polling hangs or failures. Fix this by relocating the malloc and bss to the usable 7/8 region of DDR and is fully ECC-safe. This change ensures reliable ddr address operation and prevents unintended memory corruption. Signed-off-by: Dinesh Maniyam <dinesh.mani...@intel.com> --- configs/socfpga_agilex5_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 4ac0a5d9b99..01c5ac88015 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -12,7 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" CONFIG_DM_RESET=y CONFIG_SPL_STACK=0x7d000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xbff00000 +CONFIG_SPL_BSS_START_ADDR=0x9ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y @@ -42,7 +42,7 @@ CONFIG_HANDOFF=y CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000 +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y -- 2.26.2
