From: Quentin Schulz <quentin.sch...@cherry.de> The u2phy1_host port is the part of the USB PHY1 (namely the HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG controller (dwc3), which we do use.
The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply disable the USB2.0 controllers and associated part in USB2.0 PHY. No intended functional change. [1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf Chapter 2 USB2.0 PHY Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Signed-off-by: Quentin Schulz <quentin.sch...@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechow...@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a...@thaumatec.com Signed-off-by: Heiko Stuebner <he...@sntech.de> [ upstream commit: 3373af1d76bacd054b37f3e10266dd335ce425f8 ] (cherry picked from commit 97640da1f41d022484c1a4725bed943a5ae56073) --- dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi index 314d9dfdba5732c574283271fdb1e8f8ed5405ca..587e89d7fc5e4267b877cbf8c9474bbf97b7b7af 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi @@ -585,10 +585,6 @@ u2phy1_otg: otg-port { status = "okay"; }; - - u2phy1_host: host-port { - status = "okay"; - }; }; &usbdrd3_1 { @@ -622,11 +618,3 @@ vdd2-supply = <&vcc3v3_sys>; }; }; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; -- 2.50.1
