Convert the PXA1908 platform and its coreprimevelte board to OF_UPSTREAM
and enable the few drivers found in the upstream DTS.
Signed-off-by: Duje Mihanović <d...@dujemihanovic.xyz>
---
Important note: The PXA1908 DTs were merged into Linux during the v6.17
merge window. Thus, it depends on the v6.17-rc1-dts subtree tag being
merged. I'm sending this now just so that any eventual feedback can be
addressed in time for the v6.17 release.
---
arch/arm/Kconfig | 1 +
.../dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi | 20 ++++
arch/arm/dts/pxa1908-samsung-coreprimevelte.dts | 74 --------------
arch/arm/dts/pxa1908.dtsi | 106 ---------------------
configs/coreprimevelte_defconfig | 7 +-
5 files changed, 27 insertions(+), 181 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index
40368abc297ec4748b3b3731e485dca3b53b8897..2a3ff2108c1d2255c47604d21783e6548773e68f
100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -882,6 +882,7 @@ config ARCH_MMP
select OF_CONTROL
select SAVE_PREV_BL_FDT_ADDR
select SAVE_PREV_BL_INITRAMFS_START_ADDR
+ imply OF_UPSTREAM
config ARCH_LPC32XX
bool "NXP LPC32xx platform"
diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi
b/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi
new file mode 100644
index
0000000000000000000000000000000000000000..2e5ec5c597d426e6394a0203eeda68939ca726f5
--- /dev/null
+++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Duje Mihanović <d...@dujemihanovic.xyz>
+ */
+
+/ {
+ pxa,rev-id = <3928 0>, <3928 1>, <3928 2>;
+
+ memory@0 {
+ reg = <0 0x1000000 0 0x3f000000>;
+ };
+};
+
+&uart0 {
+ clock-frequency = <14745600>;
+};
+
+&pmx {
+ compatible = "marvell,pxa1908-padconf", "pinctrl-single";
+};
diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
deleted file mode 100644
index
588e39e92650f9217e02bb332dcdcd5f74cc7fce..0000000000000000000000000000000000000000
--- a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-#include "pxa1908.dtsi"
-
-/ {
- pxa,rev-id = <3928 2>;
- model = "Samsung Galaxy Core Prime VE LTE";
- compatible = "samsung,coreprimevelte", "marvell,pxa1908";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- stdout-path = "serial0:115200n8";
-
- /* S-Boot places the initramfs here */
- linux,initrd-start = <0x4d70000>;
- linux,initrd-end = <0x5000000>;
-
- fb0: framebuffer@17177000 {
- compatible = "simple-framebuffer";
- reg = <0 0x17177000 0 (480 * 800 * 4)>;
- width = <480>;
- height = <800>;
- stride = <(480 * 4)>;
- format = "a8r8g8b8";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0 0x1000000 0 0x3f000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- framebuffer@17000000 {
- reg = <0 0x17000000 0 0x1800000>;
- no-map;
- };
-
- gpu@9000000 {
- reg = <0 0x9000000 0 0x1000000>;
- };
-
- /* Communications processor, aka modem */
- cp@5000000 {
- reg = <0 0x5000000 0 0x3000000>;
- };
-
- cm3@a000000 {
- reg = <0 0xa000000 0 0x80000>;
- };
-
- seclog@8000000 {
- reg = <0 0x8000000 0 0x100000>;
- };
-
- ramoops@8100000 {
- compatible = "ramoops";
- reg = <0 0x8100000 0 0x40000>;
- record-size = <0x8000>;
- console-size = <0x20000>;
- max-reason = <5>;
- };
- };
-};
diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi
deleted file mode 100644
index
e8ec2606c2515ee2031004ab3102fec37b7d4b87..0000000000000000000000000000000000000000
--- a/arch/arm/dts/pxa1908.dtsi
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "Marvell Armada PXA1908";
- compatible = "marvell,pxa1908";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0 0>;
- enable-method = "psci";
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0 1>;
- enable-method = "psci";
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0 2>;
- enable-method = "psci";
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0 3>;
- enable-method = "psci";
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gic: interrupt-controller@d1df9000 {
- compatible = "arm,gic-400";
- reg = <0 0xd1df9000 0 0x1000>,
- <0 0xd1dfa000 0 0x2000>,
- /* The subsequent registers are guesses. */
- <0 0xd1dfc000 0 0x2000>,
- <0 0xd1dfe000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- apb@d4000000 {
- compatible = "simple-bus";
- reg = <0 0xd4000000 0 0x200000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xd4000000 0x200000>;
-
- uart0: serial@17000 {
- compatible = "mrvl,mmp-uart",
"intel,xscale-uart";
- reg = <0x17000 0x1000>;
- clock-frequency = <14745600>;
- reg-shift = <2>;
- };
-
- uart1: serial@18000 {
- compatible = "mrvl,mmp-uart",
"intel,xscale-uart";
- reg = <0x18000 0x1000>;
- clock-frequency = <14745600>;
- reg-shift = <2>;
- };
-
- uart2: serial@36000 {
- compatible = "mrvl,mmp-uart",
"intel,xscale-uart";
- reg = <0x36000 0x1000>;
- clock-frequency = <117000000>;
- reg-shift = <2>;
- };
- };
- };
-};
diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig
index
05116669200b3f1393518c8f9d1d0d5b9f90db6f..c4cd9d2dc01e49d4f02c3e8f6ccfdcfe18909915
100644
--- a/configs/coreprimevelte_defconfig
+++ b/configs/coreprimevelte_defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MMP=y
CONFIG_TEXT_BASE=0x1000000
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/mmp/pxa1908-samsung-coreprimevelte"
CONFIG_TARGET_COREPRIMEVELTE=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_ARMV8_PSCI=y
@@ -14,5 +14,10 @@ CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
CONFIG_OF_BOARD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_SIMPLE=y
---
base-commit: a80bfe1a849a5f2b63c55057fd4f77db89a19fe6
change-id: 20250816-pxa1908-upstream-5963cfe7cb15
Best regards,
--
Duje Mihanović <d...@dujemihanovic.xyz>
