> -----Original Message-----
> From: Ng, Boon Khai <boon.khai...@altera.com>
> Sent: Thursday, August 14, 2025 11:18 AM
> To: U-boot Openlist <u-boot@lists.denx.de>
> Cc: Tom Rini <tr...@konsulko.com>; Simon Glass <s...@chromium.org>;
> Marek Vasut <ma...@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Maniyam, Dinesh
> <dinesh.mani...@altera.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yusla...@altera.com>; Lim, Jit Loon <jit.loon....@altera.com>;
> Ng, Boon Khai <boon.khai...@altera.com>; Kathpalia, Tanmay
> <tanmay.kathpa...@altera.com>; Ilias Apalodimas
> <ilias.apalodi...@linaro.org>; Jerome Forissier
> <jerome.foriss...@linaro.org>; Rao, Mahesh <mahesh....@altera.com>
> Subject: [PATCH v2 3/3] configs: agilex5: Enable config SPL_SYS_DCACHE_OFF
>
> Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL
>
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpa...@altera.com>
> Signed-off-by: Boon Khai Ng <boon.khai...@altera.com>
> ---
> configs/socfpga_agilex5_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index 33a6221979a..8c31dcfea11 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -45,6 +45,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
> CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
> CONFIG_SPL_CACHE=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> CONFIG_SPL_MTD=y
> CONFIG_SPL_SPI_FLASH_MTD=y
> CONFIG_SPL_SPI_LOAD=y
> --
> 2.35.3
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
