On 2025/7/14 07:33, Jonas Karlman wrote:
Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.

Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>

Thanks,
- Kever
---
  drivers/clk/rockchip/clk_px30.c | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index ad7e1c0f2460..b5054e84c326 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1360,6 +1360,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong 
rate)
        case SCLK_GMAC_RMII:
                ret = px30_mac_set_speed_clk(priv, rate);
                break;
+       /* Might occur in cru assigned-clocks, can be ignored here */
+       case SCLK_GPU:
+               break;
  #endif
        default:
                return -ENOENT;
@@ -1726,6 +1729,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong 
rate)
        case SCLK_UART0_PMU:
                ret = px30_pmu_uart0_set_clk(priv, rate);
                break;
+       /* Might occur in pmucru assigned-clocks, can be ignored here */
+       case SCLK_WIFI_PMU:
+               break;
        default:
                return -ENOENT;
        }

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