Re: [PATCH 4/8] rockchip: rk3528: Disable USB3OTG U3 port early

[Kever Yang]

On 2025/7/31 07:52, Jonas Karlman wrote:

The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).

Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.

Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.

Signed-off-by: Jonas Karlman <jo...@kwiboo.se>

Reviewed-by: Kever Yang <kever.y...@rock-chips.com>

Thanks,
- Kever

---
  arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c 
b/arch/arm/mach-rockchip/rk3528/rk3528.c
index 4892ff6ba9d2..f9bfc445b857 100644
--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -9,6 +9,9 @@
  #include <asm/arch-rockchip/bootrom.h>
  #include <asm/arch-rockchip/hardware.h>

+#define VPU_GRF_BASE 0xff340000

+#define USB3OTG_CON1                   0x44
+
  #define FIREWALL_DDR_BASE             0xff2e0000
  #define FW_DDR_MST6_REG                       0x58
  #define FW_DDR_MST7_REG                       0x5c
@@ -69,6 +72,9 @@ int arch_cpu_init(void)
        val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
        writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);

+ /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */

+       writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
+
        return 0;
  }