Hi,
On 16/10/2025 15:27, Richard Genoud wrote:
Introduce per SoC capabilities in sunxi_nand.c
This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.
Start with the ECC strength table.
No functional change.
Looks good, just one nit below:
Signed-off-by: Richard Genoud <[email protected]>
---
drivers/mtd/nand/raw/sunxi_nand.c | 18 ++++++++++++++++--
drivers/mtd/nand/raw/sunxi_nand.h | 10 ++++++++++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c
b/drivers/mtd/nand/raw/sunxi_nand.c
index 000ebd0439f1..3f30077b3d15 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -149,6 +149,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct
nand_chip *nand)
* @clk_rate: NAND controller current clock rate
* @chips: a list containing all the NAND chips attached to
* this NAND controller
> + * @caps: NAND Controller capabilities
Please indent the description to line up with the other ones.
With that fixed:
Reviewed-by: Andre Przywara <[email protected]>
Cheers,
Andre
*/
struct sunxi_nfc {
struct nand_hw_control controller;
@@ -159,6 +160,7 @@ struct sunxi_nfc {
unsigned long assigned_cs;
unsigned long clk_rate;
struct list_head chips;
+ const struct sunxi_nfc_caps *caps;
};
static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
@@ -1270,6 +1272,9 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct
mtd_info *mtd,
struct nand_ecc_ctrl *ecc)
{
static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+ struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
struct sunxi_nand_hw_ecc *data;
struct nand_ecclayout *layout;
int nsectors;
@@ -1292,7 +1297,7 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct
mtd_info *mtd,
}
/* Add ECC info retrieval from DT */
- for (i = 0; i < ARRAY_SIZE(strengths); i++) {
+ for (i = 0; i < nfc->caps->nstrengths; i++) {
if (ecc->strength <= strengths[i]) {
/*
* Update ecc->strength value with the actual strength
@@ -1303,7 +1308,7 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct
mtd_info *mtd,
}
}
- if (i >= ARRAY_SIZE(strengths)) {
+ if (i >= nfc->caps->nstrengths) {
dev_err(mtd->dev, "unsupported strength\n");
ret = -ENOTSUPP;
goto err;
@@ -1681,6 +1686,10 @@ static int sunxi_nand_probe(struct udevice *dev)
if (!nfc->regs)
return -EINVAL;
+ nfc->caps = (const struct sunxi_nfc_caps *)dev_get_driver_data(dev);
+ if (!nfc->caps)
+ return -EINVAL;
+
ret = reset_get_bulk(dev, &rst_bulk);
if (!ret)
reset_deassert_bulk(&rst_bulk);
@@ -1702,9 +1711,14 @@ static int sunxi_nand_probe(struct udevice *dev)
return 0;
}
+static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
+ .nstrengths = 9,
+};
+
static const struct udevice_id sunxi_nand_ids[] = {
{
.compatible = "allwinner,sun4i-a10-nand",
+ .data = (unsigned long)&sunxi_nfc_a10_caps,
},
{ }
};
diff --git a/drivers/mtd/nand/raw/sunxi_nand.h
b/drivers/mtd/nand/raw/sunxi_nand.h
index 59803ccc9f22..80fbc8df0090 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.h
+++ b/drivers/mtd/nand/raw/sunxi_nand.h
@@ -153,4 +153,14 @@
#define NFC_MAX_CS 7
+/*
+ * NAND Controller capabilities structure: stores NAND controller capabilities
+ * for distinction between compatible strings.
+ *
+ * @nstrengths: Number of element of ECC strengths array
+ */
+struct sunxi_nfc_caps {
+ unsigned int nstrengths;
+};
+
#endif
