Hi,
On 20/10/2025 9:34 pm, Brian Sune wrote:
Since U-Boot 2025.07 pure SD Card
boot no longer works. Now Altera released 2025.07
shows the different on the u-boot files.
After testing, the major root case is
get_managers_addr. And this patch fix the
SD boot stall via pulling from offical.
Signed-off-by: Brian Sune<[email protected]>
---
arch/arm/mach-socfpga/misc.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 76747c2196a..c54f5e32454 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -178,7 +178,10 @@ int arch_cpu_init(void)
* timeout value is still active which might too short for Linux
* booting.
*/
+#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))
hw_watchdog_init();
+#endif
This is intended for internal use and should be removed.
#else
/*
* If the HW watchdog is NOT enabled, make sure it is not running,
@@ -223,8 +226,16 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int
argc,
U_BOOT_CMD(bridge, 3, 1, do_bridge,
"SoCFPGA HPS FPGA bridge control",
- "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1),
FPGA-to-HPS (Bit 2) bridges\n"
- "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit
1), FPGA-to-HPS (Bit 2) bridges\n"
+ "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1),
FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n"
+ "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit
1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5)
bridges\n"
+ "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n"
+ "For example:\n"
+ "1) To enable and disable all bridges (command without mask):\n"
+ " a) bridge enable\n"
+ " b) bridge disable\n"
+ "2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command
with mask):\n"
+ " a) bridge enable 0x3\n"
+ " b) bridge disable 0x3\n"
""
);
@@ -261,6 +272,17 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
+ if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) &&
!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
The condition for non-Agilex5 platforms should be rewritten because
|sys-mgr| has already moved to the driver model for these platforms.
+ ret = socfpga_get_base_addr("altr,sys-mgr",
+ &socfpga_sysmgr_base);
+ if (ret)
+ hang();
+ }
+
+ if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) ||
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M))
+ ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+ &socfpga_clkmgr_base);
Similarly, the section for Agilex and Agilex7M using |clkmgr| can be
removed, as both now use the driver model.
else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
The N5X section should be updated as: "if
(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))"
The remaining part of the function can remain intact.
ret = socfpga_get_base_addr("intel,n5x-clkmgr",
&socfpga_clkmgr_base);
We’ve already tested the above changes and they work as expected.
Thanks.
Tien Fong
