In A733 SoC, the GPIO IP block has changed its arrangement, so initial GPIO base address and port size need to be adjusted.
Introduce new SUNXI_NEW2_PINCTRL in order to reuse the driver in future. There is no PA port exist in A733, but introducing a virtual one as offset 0x80, and with the port size 0x80, it will iterate other port correctly starting from PB as offset 0x100. Signed-off-by: Yixun Lan <[email protected]> --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/gpio/Kconfig | 7 +++++++ drivers/gpio/sunxi_gpio.c | 12 ++++++++++-- include/sunxi_gpio.h | 11 ++++++++++- 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d16ffddf482..81dea29964a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -560,6 +560,7 @@ config MACH_SUN55I_A523 config MACH_SUN60I_A733 bool "sun60i (Allwinner A733)" select ARM64 + select SUNXI_NEW2_PINCTRL select FIT select SPL_LOAD_FIT if SPL select SUPPORT_SPL diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index db077e472a8..8a578b872c2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -426,6 +426,13 @@ config SUNXI_NEW_PINCTRL The Allwinner D1 and other new SoCs use a different register map for the GPIO block, which we need to know about in the SPL. +config SUNXI_NEW2_PINCTRL + bool + depends on SUNXI_GPIO + ---help--- + The Allwinner A733 SoCs use a different register map + for the GPIO block, which we need to know about in the SPL. + config XILINX_GPIO bool "Xilinx GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 094c45a6927..6fa74e5c599 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -38,18 +38,26 @@ #define GPIO_DAT_REG_OFFSET 0x10 -#define GPIO_DRV_REG_OFFSET 0x14 /* Newer SoCs use a slightly different register layout */ #ifdef CONFIG_SUNXI_NEW_PINCTRL /* pin drive strength: 4 bits per pin */ +#define GPIO_DRV_REG_OFFSET 0x14 #define GPIO_DRV_INDEX(pin) ((pin) / 8) #define GPIO_DRV_OFFSET(pin) (((pin) % 8) * 4) #define GPIO_PULL_REG_OFFSET 0x24 +#elif CONFIG_SUNXI_NEW2_PINCTRL +#define GPIO_DRV_REG_OFFSET 0x20 +#define GPIO_DRV_INDEX(pin) ((pin) / 8) +#define GPIO_DRV_OFFSET(pin) (((pin) % 8) * 4) + +#define GPIO_PULL_REG_OFFSET 0x30 + #else /* older generation pin controllers */ /* pin drive strength: 2 bits per pin */ +#define GPIO_DRV_REG_OFFSET 0x14 #define GPIO_DRV_INDEX(pin) ((pin) / 16) #define GPIO_DRV_OFFSET(pin) (((pin) % 16) * 2) @@ -64,7 +72,7 @@ static void* BANK_TO_GPIO(int bank) void *pio_base; if (bank < SUNXI_GPIO_L) { - pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE; + pio_base = (void *)(uintptr_t)(SUNXI_PIO_BASE + SUNXI_PIO_OFFSET); } else { pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE; bank -= SUNXI_GPIO_L; diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index 12b54c8dda4..ba8e5428900 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -19,7 +19,7 @@ #elif defined(CONFIG_SUN50I_GEN_H6) #define SUNXI_PIO_BASE 0x0300b000 #define SUNXI_R_PIO_BASE 0x07022000 -#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#elif defined(CONFIG_SUNXI_GEN_NCAT2) || defined(CONFIG_SUNXI_NEW2_PINCTRL) #define SUNXI_PIO_BASE 0x02000000 #define SUNXI_R_PIO_BASE 0x07022000 #else @@ -27,6 +27,12 @@ #define SUNXI_R_PIO_BASE 0x01f02c00 #endif +#if CONFIG_SUNXI_NEW2_PINCTRL +#define SUNXI_PIO_OFFSET 0x80 /* offset for virtual PA port */ +#else +#define SUNXI_PIO_OFFSET 0x00 +#endif + /* * sunxi has 9 banks of gpio, they are: * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 @@ -172,6 +178,9 @@ enum sunxi_gpio_number { #ifdef CONFIG_SUNXI_NEW_PINCTRL #define SUNXI_PINCTRL_BANK_SIZE 0x30 #define SUNXI_GPIO_DISABLE 0xf +#elif CONFIG_SUNXI_NEW2_PINCTRL + #define SUNXI_PINCTRL_BANK_SIZE 0x80 + #define SUNXI_GPIO_DISABLE 0xf #else #define SUNXI_PINCTRL_BANK_SIZE 0x24 #define SUNXI_GPIO_DISABLE 0x7 -- 2.51.2
