On Sun, Nov 30, 2025 at 09:45:15PM +0000, Yixun Lan wrote: > In A733 SoC, the GPIO IP block has changed its arrangement, so initial > GPIO base address and bank size need to be adjusted. > > Introduce new SUNXI_NEW2_PINCTRL in order to reuse the driver in future. > > There is no PA bank exist in A733, but introducing a virtual one as offset > 0x80, and with the bank size 0x80, it will iterate other bank correctly > starting from PB as offset 0x100. > > Signed-off-by: Yixun Lan <[email protected]>
So, looking at: commit 452369cd0c636123321d021298b4bc35a34f4941 Author: Andre Przywara <[email protected]> Date: Tue Sep 6 12:12:50 2022 +0100 pinctrl: sunxi: add new D1 pinctrl support For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy interfaces. Add a new Kconfig symbol to differenciate between the two generations of pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Sam Edwards <[email protected]> Tested-by: Sam Edwards <[email protected]> Tested-by: Samuel Holland <[email protected]> Is there some way to abstract things so that again, non-SPL has a single driver, and for SPL we can just hard-code a few things? -- Tom
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