J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The PCIe1 instance is used for PCIe endpoint boot. Enable the configs required for PCIe boot on the J784S4 platform.
Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence Torrent PHY, and MMIO multiplexer. These are required to configure the SERDES lanes at the R5 SPL stage for PCIe endpoint operation. Signed-off-by: Hrushikesh Salunke <[email protected]> --- configs/j784s4_evm_r5_defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index cc340a2fe76..a69a253ad12 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -52,9 +52,16 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x80800000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tiboot3.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -122,6 +129,12 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y +CONFIG_PCIE_CDNS_TI_EP=y +CONFIG_SPL_PHY=y +CONFIG_SPL_PHY_CADENCE_TORRENT=y +CONFIG_SPL_PHY_J721E_WIZ=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y -- 2.34.1
