Yuslaimi, Alif Zakuan <[email protected]> 於 2025年12月4日週四 上午9:11寫道： > > Hi, > > On 4/12/2025 5:02 am, Sune Brian wrote: > > [CAUTION: This email is from outside your organization. Unless you trust > > the sender, do not click on links or open attachments as it may be a > > fraudulent email attempting to steal your information and/or compromise > > your computer.] > > > > Ralph Siemsen <[email protected]> 於 2025年12月4日週四 上午4:52寫道： > >> > >> Hi Brian, > >> > >> On Wed, Dec 3, 2025 at 1:17 PM Sune Brian <[email protected]> wrote: > >> > >>> But did you disable also all "CYCLIC" as well? > >> > >> I have "CONFIG_CYCLIC is not set" which disables all the others. > >> > >> I also have another patch to disable the watchdog, adapted from [1]. > >> This didn't seem to make any difference (but my ram calibration > >> doesn't take very long). > >> > >> [1] > >> https://lore.kernel.org/all/[email protected]/ > >> > > > > Hi Ralph, > > > > I do diff the mainstream and Altera trunk. > > I cam repeat the same behavior on altera trunk when all WDT CYCLIC turned > > off. > > > > I plan to investigate under another board. > > TBH if it is board specific case then there is nothing harm to simply > > turn on CYCLIC or WDT. > > But the truth is that Altera trunk force using designware WDT by default. > > Because under distro I do full "memtester" and "stressapptest". > > Nothing really fails on those two. > > > > I have tried to disable all WDT and CYCLIC configs on both Altera trunk > and mainline U-Boot on my side. > > I made some changes to the standard socfpga_cyclone5_defconfig as well > as the common Kconfig to really disable all watchdog configs. > > I cannot replicate the issue on both cases, I am able to boot via RAM > through ARM debugger, as well as through MMC boot after triggering reset > in Linux. > > I am using our Cyclone V SoC Development Kit, details of the board can > be found here > > [1] > https://www.rocketboards.org/foswiki/Documentation/AlteraSoCDevelopmentBoard > > I am thinking this could be related to the power supply not being fully > stable before SDRAM calibration, perhaps you could try other reset > methods, such as cold/warm reset, or power cycling the board and see if > there is any difference compared to using the physical reset switch key? > > Thanks, > Alif > > >>> 3) I use socfpga_cyclone5_defconfig and only change minimum settings > >>> that I needs. > >>> From this issue mentioned to current day. > >> > >> Then it sounds like it is a recent issue... hmm... I'm currently on > >> 2025.10 release version (plus some cherry-picks). I'll give a try on > >> master/next once I get some other things stabilised... > >> > >> Regards, > >> Ralph > > > > The major reason is the ECC on mainstream is completely missing. > > BTW [1] I do manually inserted and test no luck on that. > > > > Yet still thank you for the help. > > > > Brian >
Hi Alif, I think almost 90% or even 95% above board only uses 1GB socdk as well. I am undergoing a deep investigation. Cyclone V SoC FPGA boards also do not have issues w/o WDT CYCLIC. The issue happened on 2GB variant boards. If any parties or users happen to have 2GB please do point out it is OK. If not it is a 32bit bug on driver or other files. Calibration time is indeed longer. No time shift is not a solution or inherent problem here. 2x512x16 ddr die is used to introduce a signed possible issue perhase. aka 0x8000_0000 Thanks, Brian
