When exiting a low power mode with DDR self-refresh, we can directly resume after DDR setup is done. Call the common function to resume.
Swap order of setup_qos() and spl_enable_cache(). setup_qos() is required for LPM resume but spl_enable_cache() is not required. There is no dependency between the two. Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]> --- arch/arm/mach-k3/am62px/am62p5_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index a74fe3d23d7c4b66ac95aa5a01c2a32a586e9ced..64e146365929f69803217ca0cb9f46eaefae9529 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -253,9 +253,19 @@ void board_init_f(ulong dummy) enable_mcu_esm_reset(); } + setup_qos(); + + if (wkup_ctrl_is_lpm_exit()) { + u64 meta_data_addr; + + ret = wkup_r5f_am62_lpm_meta_data_addr(&meta_data_addr); + if (ret) + panic("Failed to get LPM meta data address %d\n", ret); + lpm_resume_from_ddr(meta_data_addr); + } + spl_enable_cache(); - setup_qos(); debug("am62px_init: %s done\n", __func__); fixup_a53_cpu_freq_by_speed_grade(); -- 2.51.0
