On Tue, Jan 13, 2026 at 09:52:13AM +0530, Balaji Selvanathan wrote: > From: Swathi Tamilselvan <[email protected]> > > Add clock gate definitions and entries for QUP (Qualcomm Universal > Peripheral) serial engine clocks across all four wrappers on SA8775P. > This enables proper clock management for I2C, SPI, and UART > peripherals connected to the QUP blocks. > > This resolves the "unknown clock ID 133" error for UART10 and > provides complete QUP clock infrastructure for the platform. > > Signed-off-by: Swathi Tamilselvan <[email protected]> > Signed-off-by: Balaji Selvanathan <[email protected]> > --- > drivers/clk/qcom/clock-sa8775p.c | 54 ++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+)
Acked-by: Sumit Garg <[email protected]> -Sumit > > diff --git a/drivers/clk/qcom/clock-sa8775p.c > b/drivers/clk/qcom/clock-sa8775p.c > index 527cecf5c82..5a6fbd417ff 100644 > --- a/drivers/clk/qcom/clock-sa8775p.c > +++ b/drivers/clk/qcom/clock-sa8775p.c > @@ -18,6 +18,31 @@ > #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 > #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 > > +#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) > +#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) > +#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) > +#define GCC_QUPV3_WRAP0_S3_CLK_ENA_BIT BIT(13) > +#define GCC_QUPV3_WRAP0_S4_CLK_ENA_BIT BIT(14) > +#define GCC_QUPV3_WRAP0_S5_CLK_ENA_BIT BIT(15) > + > +#define GCC_QUPV3_WRAP1_S0_CLK_ENA_BIT BIT(22) > +#define GCC_QUPV3_WRAP1_S1_CLK_ENA_BIT BIT(23) > +#define GCC_QUPV3_WRAP1_S2_CLK_ENA_BIT BIT(24) > +#define GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT BIT(25) > +#define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26) > +#define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27) > +#define GCC_QUPV3_WRAP1_S6_CLK_ENA_BIT BIT(27) > + > +#define GCC_QUPV3_WRAP2_S0_CLK_ENA_BIT BIT(4) > +#define GCC_QUPV3_WRAP2_S1_CLK_ENA_BIT BIT(5) > +#define GCC_QUPV3_WRAP2_S2_CLK_ENA_BIT BIT(6) > +#define GCC_QUPV3_WRAP2_S3_CLK_ENA_BIT BIT(7) > +#define GCC_QUPV3_WRAP2_S4_CLK_ENA_BIT BIT(8) > +#define GCC_QUPV3_WRAP2_S5_CLK_ENA_BIT BIT(9) > +#define GCC_QUPV3_WRAP2_S6_CLK_ENA_BIT BIT(29) > + > +#define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25) > + > static ulong sa8775p_set_rate(struct clk *clk, ulong rate) > { > struct msm_clk_priv *priv = dev_get_priv(clk->dev); > @@ -50,6 +75,35 @@ static const struct gate_clk sa8775p_clks[] = { > GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), > GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), > GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), > + > + /* QUP Wrapper 0 clocks */ > + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S3_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S4_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x4b008, > GCC_QUPV3_WRAP0_S5_CLK_ENA_BIT), > + > + /* QUP Wrapper 1 clocks (includes uart10) */ > + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S0_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S1_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S2_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT), /* uart10 */ > + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x4b008, > GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x4b018, > GCC_QUPV3_WRAP1_S6_CLK_ENA_BIT), > + > + /* QUP Wrapper 2 clocks */ > + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S0_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S1_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S2_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S3_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S4_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x4b010, > GCC_QUPV3_WRAP2_S5_CLK_ENA_BIT), > + GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x4b018, > GCC_QUPV3_WRAP2_S6_CLK_ENA_BIT), > + > + /* QUP Wrapper 3 clocks */ > + GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, > GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), > }; > > static int sa8775p_enable(struct clk *clk) > -- > 2.34.1 >
