On Wed, 10 Dec 2025 16:54:52 +0100, Loic Poulain wrote:
> When 'max-clk' is not specified, the SDHCI core retrieves the base clock
> from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
> is unreliable on MSM SDHCI controllers, as noted by the Linux driver
> using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
> is only 8 bits wide and cannot represent base clocks above 255 MHz.
>
> On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
> 384 MHz, but the capabilities register reports 200 MHz. As a result,
> the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
> the intended ~52 MHz. This overclocking can cause sporadic CRC errors
> with certain eMMC.
>
> [...]
Applied, thanks!
[1/3] mmc: msm_sdhci: Fix incorrect divider calculation for SDCLK
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/edd1fb0c3695
[2/3] clk/qcom: qcm2290: Add SDCC1 apps clock frequency table
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/3ddc67573fab
[3/3] mmc: msm_sdhci: Add DLL control hook to disable DLL below 100 MHz
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/338c4b820804
Best regards,
--
// Casey (she/they)
